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JK FLIPFLOP
JK FLIPFLOPDFF USING JKFF
DFF USING JKFFDFF USING SRFF
DFF USING SRFF4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN countercircuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0MUX with counter
MUX with counter4 bit bidirectional shift register
4 bit bidirectional shift register3 x 8 DECODER
3 x 8 DECODER2 to 4 Decoder
2 to 4 DecoderIMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)1 to 16 DEMUX
1 to 16 DEMUX1 to 2 DEMUX
1 to 2 DEMUX16 to 1 MUX
16 to 1 MUXMOD 12 COUNTER
MOD 12 COUNTER16 to 1 MUX
16 to 1 MUXDistributive law of
Distributive law ofNOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOPJK FLIPFLOP
JK FLIPFLOPNAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOPSR FLIPFLOP
SR FLIPFLOPD FLIPFLOP
D FLIPFLOPTFF
TFFT FLIPFLOP
T FLIPFLOPTFF
TFFDFF USING TFF
DFF USING TFFTFF USING DFF
TFF USING DFFTFF USING JKFF
TFF USING JKFFSRFF using DFF
SRFF using DFFTFF USING SRFF
TFF USING SRFFJKFF using SRFF
JKFF using SRFFSRFF USING TFF
SRFF USING TFFJKFF USING DFF
JKFF USING DFFJKFF Using TFF
JKFF Using TFF4 bit ripple counter
4 bit ripple counter4 bit ripple down counter
4 bit ripple down counterMOD 7 COUNTER
MOD 7 COUNTERMOD 7 COUNTER
MOD 7 COUNTER4 bit synchronous counter
4 bit synchronous counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter4 bit synchronous down counter
4 bit synchronous down counter1 to 8 DEMUX
1 to 8 DEMUXSRFF USING JKFF
SRFF USING JKFF4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER32 TO 1 MUX USING 4 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUXNAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUXUntitled
Untitled3 bit binary counter
3 bit binary countermod-6 unit distance counter
mod-6 unit distance counter4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTERSIPO
SIPOPISO
PISOPIPO
PIPOSISO
SISOsequence generator using counter
sequence generator using counterBCD to Decimal Decoder
BCD to Decimal DecoderOctal to Binary Encoder
Octal to Binary Encoder2 x 1 ENCODER
2 x 1 ENCODER8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER4 x 2 ENCODER
4 x 2 ENCODER1 x 2 DECODER
1 x 2 DECODER4 to 2 priority encoder
4 to 2 priority encoderBCD to 7 segment decoder
BCD to 7 segment decoderAND gate
AND gateOR USING 2 TO 1 MUX
OR USING 2 TO 1 MUXNOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUXdecimal to bcd encoder
decimal to bcd encoder1 to 2 DEMUX
1 to 2 DEMUXNOR GATE
NOR GATEBoolean laws of addition
Boolean laws of addition2 to 1 multiplexer
2 to 1 multiplexer4 to 1 multiplexer
4 to 1 multiplexer8 to 1 mux
8 to 1 muxEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUXEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUXEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUXUntitled
UntitledEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX24 TO 1 MUX USING 1 MUX
24 TO 1 MUX USING 1 MUX16 to 1 MUX
16 to 1 MUX16 to 1 MUX
16 to 1 MUX1 to 16 DEMUX
1 to 16 DEMUXUntitled
Untitled16 to 1 mux
16 to 1 muxAND using 2 to 1 mux
AND using 2 to 1 mux8 to 1 mux
8 to 1 mux3 bit
3 bitNOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX16 TO 1 MUX
16 TO 1 MUXUntitled
Untitled16 to 1 mux
16 to 1 mux16 TO 1 MUX
16 TO 1 MUXMOD 7 COUNTER
MOD 7 COUNTERDecimal to BCD Encoder
Decimal to BCD Encodercounter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0