project.name

Alaguraja K

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

Untitled

Untitled
Public
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SUBRACTERS

SUBRACTERS
Public
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PARITY GENERATOR AND CHECKER

PARITY GENERATOR AND CHECKER
Public
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MINTERMS(1,3,4,11,12,13,14,15)

MINTERMS(1,3,4,11,12,13,14,15)
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Untitled

Untitled
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1 TO 4 DEMULTIPLEXER

1 TO 4 DEMULTIPLEXER
Public
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full subracter using nand gate

full subracter using nand gate
Public
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ADDERS

ADDERS
Public
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d using sr flipflop

d using sr flipflop
Public
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ring counter

ring counter
Public
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decimal to bcd encoder

decimal to bcd encoder
Public
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1-6 THEOREMS OF LOGIC GATES

1-6 THEOREMS OF LOGIC GATES
Public
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Untitled

Untitled
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THEORREM 6 - 12 LOGIC GATES

THEORREM 6 - 12 LOGIC GATES
Public
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Universal Shift Register

Universal Shift Register
Public
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3 to 8 decoder

3 to 8 decoder
Public
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decimal to bcd priority encoder

decimal to bcd priority encoder
Public
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octal to binary encoder

octal to binary encoder
Public
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HALF ADDER USING NOR GATE

HALF ADDER USING NOR GATE
Public
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Untitled

Untitled
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SISO SR

SISO SR
Public
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Untitled

Untitled
Public
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4to1 mux

4to1 mux
Public
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4-bit ripple counter

4-bit ripple counter
Public
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Shift Counter

Shift Counter
Public
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BASIC GATES

BASIC GATES
Public
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bcd to decimal decoder

bcd to decimal decoder
Public
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2-bit magnitude comparitor

2-bit magnitude comparitor
Public
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MINTERMS(1,3,4,11,12,13,14,15)

MINTERMS(1,3,4,11,12,13,14,15)
Public
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up/down counter

up/down counter
Public
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mod 10 ripple counter

mod 10 ripple counter
Public
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