project.name

Alaguraja K

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

Untitled

Untitled
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SUBRACTERS

SUBRACTERS
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PARITY GENERATOR AND CHECKER

PARITY GENERATOR AND CHECKER
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MINTERMS(1,3,4,11,12,13,14,15)

MINTERMS(1,3,4,11,12,13,14,15)
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Untitled
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1 TO 4 DEMULTIPLEXER

1 TO 4 DEMULTIPLEXER
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full subracter using nand gate

full subracter using nand gate
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ADDERS

ADDERS
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d using sr flipflop

d using sr flipflop
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ring counter

ring counter
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decimal to bcd encoder

decimal to bcd encoder
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1-6 THEOREMS OF LOGIC GATES

1-6 THEOREMS OF LOGIC GATES
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THEORREM 6 - 12 LOGIC GATES

THEORREM 6 - 12 LOGIC GATES
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Universal Shift Register

Universal Shift Register
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3 to 8 decoder

3 to 8 decoder
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decimal to bcd priority encoder

decimal to bcd priority encoder
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octal to binary encoder

octal to binary encoder
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HALF ADDER USING NOR GATE

HALF ADDER USING NOR GATE
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Untitled

Untitled
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SISO SR

SISO SR
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4to1 mux

4to1 mux
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4-bit ripple counter

4-bit ripple counter
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Shift Counter

Shift Counter
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BASIC GATES

BASIC GATES
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bcd to decimal decoder

bcd to decimal decoder
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2-bit magnitude comparitor

2-bit magnitude comparitor
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MINTERMS(1,3,4,11,12,13,14,15)

MINTERMS(1,3,4,11,12,13,14,15)
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up/down counter

up/down counter
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mod 10 ripple counter

mod 10 ripple counter
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Alaguraja K is not a collaborator of any project.

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