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MUX with counter
MUX with counter
JK FLIPFLOP
JK FLIPFLOP
1 to 16 DEMUX
1 to 16 DEMUX
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
SR FLIPFLOP
SR FLIPFLOP
D FLIPFLOP
D FLIPFLOP
SRFF using DFF
SRFF using DFF
T FLIPFLOP
T FLIPFLOP
SRFF USING TFF
SRFF USING TFF
JKFF Using TFF
JKFF Using TFF
TFF USING DFF
TFF USING DFF
JKFF USING DFF
JKFF USING DFF
DFF USING TFF
DFF USING TFF
SR FLIPFLOP
SR FLIPFLOP
4 bit ripple counter
4 bit ripple counter
4 bit ripple down counter
4 bit ripple down counter
MOD 12 COUNTER
MOD 12 COUNTER
2 to 1 multiplexer
2 to 1 multiplexer
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
Ripple carry Adder
Ripple carry Adder
4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN counter
32 TO 1 MUX USING 4 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUX
3 bit
3 bit
OR USING 2 TO 1 MUX
OR USING 2 TO 1 MUX
Untitled
Untitled
4 to 1 multiplexer
4 to 1 multiplexer
Untitled
Untitled
2 to 1 multiplexer
2 to 1 multiplexer
16 TO 1 MUX
16 TO 1 MUX
24 TO 1 MUX USING 1 MUX
24 TO 1 MUX USING 1 MUX
EXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
16 TO 1 MUX
16 TO 1 MUX
16 to 1 MUX
16 to 1 MUX
Ripple carry Adder
Ripple carry Adder
BCD ADDER
BCD ADDER
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
HALF SUBTRACTOR
HALF SUBTRACTOR
GRAY TO BINARY CODE CONVERTER
GRAY TO BINARY CODE CONVERTER
HALF SUBTRACTOR-NOR NOR IMPLEMENTATION
HALF SUBTRACTOR-NOR NOR IMPLEMENTATION
FULL SUBRACTOR USING NOR GATES
FULL SUBRACTOR USING NOR GATES
FULL ADDER-NAND NAND IMPLEMENTATION
FULL ADDER-NAND NAND IMPLEMENTATION
Hlaf adder
Hlaf adder
FULL ADDER USING NOR GATES
FULL ADDER USING NOR GATES
FULL SUBRACTOR USING NOR GATES
FULL SUBRACTOR USING NOR GATES
Half subtractor using basic gates
Half subtractor using basic gates
HALF ADDER-NOR NOR GATES
HALF ADDER-NOR NOR GATES
BCD TO EXCESS-3
BCD TO EXCESS-3
4 bit synchronous counter
4 bit synchronous counter
Octal to Binary Encoder
Octal to Binary Encoder
2 to 4 Decoder
2 to 4 Decoder
JK FLIPFLOP
JK FLIPFLOP
AS adder/subtractor
AS adder/subtractor
4 to 2 priority encoder
4 to 2 priority encoder
mod-6 unit distance counter
mod-6 unit distance counter
sequence generator using counter
sequence generator using counter
3 x 8 DECODER
3 x 8 DECODER
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
HALF SUBTRACTOR-NAND NAND IMPLEMENTATION
HALF SUBTRACTOR-NAND NAND IMPLEMENTATION
OR USING 2 TO 1 MUX
OR USING 2 TO 1 MUX
FULL SUBRACTOR USING TWO HALF SUBTRACTOR
FULL SUBRACTOR USING TWO HALF SUBTRACTOR
sequence generator using counter
sequence generator using counter
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
mod-6 unit distance counter
mod-6 unit distance counter
4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTER
mod-6 unit distance counter
mod-6 unit distance counter
SISO
SISO
SIPO
SIPO
PISO
PISO
PIPO
PIPO
2 x 1 ENCODER
2 x 1 ENCODER
4 x 2 ENCODER
4 x 2 ENCODER
Octal to Binary Encoder
Octal to Binary Encoder
4 to 2 priority encoder
4 to 2 priority encoder
8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
2 x 4 DECODER
2 x 4 DECODER
16 TO 1 MUX
16 TO 1 MUX
BCD to Decimal Decoder
BCD to Decimal Decoder
16 TO 1 MUX
16 TO 1 MUX
1 to 16 DEMUX
1 to 16 DEMUX
Octal to Binary Encoder
Octal to Binary Encoder
2 to 1 multiplexer
2 to 1 multiplexer
2 to 4 Decoder
2 to 4 Decoder
16 to 1 MUX
16 to 1 MUX
IMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)
2 to 4 Decoder
2 to 4 Decoder
Half adder using minimal number of NAND gates
Half adder using minimal number of NAND gates
BANU
BANU
Boolean law of multiplication
Boolean law of multiplication
AS adder/subtractor
AS adder/subtractor
OR USING 2 TO 1 MUX
OR USING 2 TO 1 MUX
Untitled
Untitled
Untitled
Untitled
BCD ADDER
BCD ADDER
Untitled
Untitled
Half Adder
Half Adder
8 to 1 mux
8 to 1 mux
Octal to Binary Encoder
Octal to Binary Encoder
Decimal to BCD Encoder
Decimal to BCD Encoder
1 x 2 DECODER
1 x 2 DECODER
Octal to Binary Encoder
Octal to Binary Encoder
Octal to Binary Encoder
Octal to Binary Encoder
1 to 16 DEMUX
1 to 16 DEMUX
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
2 to 4 Decoder
Decimal to BCD Encoder
Decimal to BCD Encoder
BCD to 7 segment decoder
BCD to 7 segment decoder
TFF USING SRFF
TFF USING SRFF
TFF
TFF
Untitled
Untitled
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
DFF USING SRFF
DFF USING SRFF
TFF USING JKFF
TFF USING JKFF
4 bit synchronous counter
4 bit synchronous counter
4 bit synchronous down counter
4 bit synchronous down counter
4 bit synchronous counter with ripple carry
4 bit synchronous counter with ripple carry
4 bit synchronous down counter
4 bit synchronous down counter
16 to 1 MUX
16 to 1 MUX
VERFICATION OF BOOLEAN LAWS AND POSTULATES
VERFICATION OF BOOLEAN LAWS AND POSTULATES
3 bit par
3 bit par
FULL SUBTRACTOR
FULL SUBTRACTOR
3 bit binary counter
3 bit binary counter
Octal to Binary Encoder
Octal to Binary Encoder
FULL SUBTRACTOR-NAND NAND IMPLEMENTATION
FULL SUBTRACTOR-NAND NAND IMPLEMENTATION
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
4 bit ripple counter
4 bit ripple counter
MOD 7 COUNTER
MOD 7 COUNTER
4 bit synchronous down counter
4 bit synchronous down counter
MOD 7 COUNTER
MOD 7 COUNTER
1 to 16 DEMUX
1 to 16 DEMUX
JKFF using SRFF
JKFF using SRFF
BINARY TO GRAY CODE CONVERTER
BINARY TO GRAY CODE CONVERTER
EXCESS-3 TO BCD
EXCESS-3 TO BCD
AND using 2 to 1 mux
AND using 2 to 1 mux
8 to 1 mux
8 to 1 mux
SRFF USING JKFF
SRFF USING JKFF
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
4 bit bidirectional shift register
4 bit bidirectional shift register
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