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1 to 2 DEMUX
1 to 2 DEMUXFull adder
Full adder3 Bit parity generator
3 Bit parity generatorFull subtractor using NOR gates
Full subtractor using NOR gatesFull adder using NOR gate
Full adder using NOR gateBinary to Gray code coverter
Binary to Gray code coverterDecimal to BCD Encoder
Decimal to BCD Encoder4 to 1 MUX
4 to 1 MUX1 to 2 decoder
1 to 2 decoder4 to 16 Decoder
4 to 16 DecoderBoolean Posculates
Boolean PosculatesIMPLEMENTATION USING MINTERMS WITH 8:1 MUX
IMPLEMENTATION USING MINTERMS WITH 8:1 MUX8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODERIMPLEMENTATION USING MINTERMS WITH 4:1 MUX
IMPLEMENTATION USING MINTERMS WITH 4:1 MUX16 to 1 mux
16 to 1 muxSingle Bit Magnitude comparator
Single Bit Magnitude comparator1:16 DEMUX
1:16 DEMUX4 to 2 Encoder
4 to 2 Encoder3 to 8 decoder
3 to 8 decoder2 to 1 MUX using NOT gate
2 to 1 MUX using NOT gate2 to 4 Decoder
2 to 4 Decoder1:8 DEMUX
1:8 DEMUX1 to 4 DEMUX
1 to 4 DEMUXGray to binary code converter
Gray to binary code converterOctal to Binary Encoder
Octal to Binary EncoderBCD to Excess-3 converter
BCD to Excess-3 converterverification of logic gates usinEX-NOR(Y=(A'B+AB')')
verification of logic gates usinEX-NOR(Y=(A'B+AB')')Full subtrator using NAND gate
Full subtrator using NAND gateBCD to 7 segment decoder
BCD to 7 segment decoderlogic gate verification by OR gate (Y=A+B)
logic gate verification by OR gate (Y=A+B)Excess-3 to BCD convertor
Excess-3 to BCD convertorIMPLEMENTATION USING MINTERMS WITH 16:1 MUX
IMPLEMENTATION USING MINTERMS WITH 16:1 MUXlogic gates verification by AND gate (Y=A.B)
logic gates verification by AND gate (Y=A.B)3 bit parity checker
3 bit parity checkerHalf adder using NOR gate
Half adder using NOR gateHalf adder using NAND gate
Half adder using NAND gate3 to 8 decoder
3 to 8 decoderlogic gates for commutative property using addition(A+B=B+A)
logic gates for commutative property using addition(A+B=B+A)2 to 1 mux using NAND gate
2 to 1 mux using NAND gateSingle bit magnitude comparator
Single bit magnitude comparatorDistributive law
Distributive lawlogiv gate verification using NOT gate (Y=A')
logiv gate verification using NOT gate (Y=A')Consensus theorum
Consensus theorumDemorgans theorum
Demorgans theorumHalf subtractor
Half subtractorlogic gates to prove commutative property for multiplication
logic gates to prove commutative property for multiplicationlogic gates verification by using NAND gate(Y=(A.B)')
logic gates verification by using NAND gate(Y=(A.B)')verification of logic gates using EX-OR gate(Y=A'B+AB')
verification of logic gates using EX-OR gate(Y=A'B+AB')4 Bit magnitude comparator
4 Bit magnitude comparator4 Bit parity generator
4 Bit parity generatorFull substractor
Full substractor2 to 1 MUX
2 to 1 MUXIMPLEMENTATION USING MINTEMS WITH 2:1 MUX
IMPLEMENTATION USING MINTEMS WITH 2:1 MUXBCD to Decimal Decoder
BCD to Decimal Decoder4 to 2 priority encoder
4 to 2 priority encoder2 to 1 Encoder
2 to 1 EncoderAbsorption theorum
Absorption theorum4 Bit parity checker
4 Bit parity checker2 to 1 mux using OR GATE
2 to 1 mux using OR GATE1 to 2 Decoder
1 to 2 DecoderFull adder using NAND gate
Full adder using NAND gate4 to 2 priority encoder
4 to 2 priority encoder24 to 1 MUX using 8 to 1 MUX
24 to 1 MUX using 8 to 1 MUX8 to 1 mux
8 to 1 mux2 to 1 Encoder
2 to 1 Encoder32 to 1 mux using 4 to 1 mux
32 to 1 mux using 4 to 1 mux2 Bit magnitude comparator
2 Bit magnitude comparatorlogic gates verification using NOR gate(Y=(A+B)')
logic gates verification using NOR gate(Y=(A+B)')Associative property
Associative propertyHalf adder
Half adderHalf subtractor using NAND gate
Half subtractor using NAND gateHalf subtractor using NOR gate
Half subtractor using NOR gate