project.name

Hersh Vitekar

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

synchronous counter

synchronous counter
Public
project.name

Flip flop

Flip flop
Public
project.name

Counters using Flip Flops

Counters using Flip Flops
Public
project.name

synchronous counter

synchronous counter
Public
project.name

synchronous counter

synchronous counter
Public
project.name

synchronous counter

synchronous counter
Public
project.name

MUX

MUX
Public
project.name

SISO/SIPO/PIPO/PISO Registers

SISO/SIPO/PIPO/PISO Registers
Public
project.name

SISO/SIPO/PIPO/PISO Registers

SISO/SIPO/PIPO/PISO Registers
Public
project.name

synchronous counter

synchronous counter
Public
project.name

Implementation of 16:1 MUX using 8:1 MUX

Implementation of 16:1 MUX using 8:1 MUX
Public
project.name

16:1 mux

16:1 mux
Public
project.name

16:1 MUX

16:1 MUX
Public
project.name

MUX

MUX
Public
project.name

JK FLIP FLOP

JK FLIP FLOP
Public
project.name

4 bit comparator final

4 bit comparator final
Public
project.name

Synchronus counters

Synchronus counters
Public
project.name

Implementation of 16:1 MUX using 8:1 MUX

Implementation of 16:1 MUX using 8:1 MUX
Public
project.name
No result image
Hersh Vitekar doesn't have any favourites.

1:16 decoder

1:16 decoder
Public
project.name