16 BIT PARITY CHECKER

FULL ADDER

FULL SUBTRACTOR

FULL SUBTRACTOR

4 bit MC

3 Parity Generator

4 BIT PARITY GENERATOR

2 to 1 MUX using OR Gate

1:16 DEMUX

PARALLEL in PARALLEL out

parallel in serial out

2 to 1 MUX using EXOR gate

1 to 2 DEMUX

2 to 1 Encoder

4 to 2 Encoder

4 to 16 decoder

1 to 4 DEMUX

IMPLEMENTATION using MINTERMS with 8 to 1 MUX

Consenses theorem

16 BIT Parity Generator

Decimal to BCD Encoder

Half Adder using NAND Gate

IMPLEMENTATION USING MINTERMS WITH 4:1 MUX

Full Subtractor using NAND Gate

1 to 2 decoder

4 Bit Excess 3 to BCD

4 Bit GRAY to BINARY

DISTRIBUTIVE

AB+BC+B`c=AB+C

Shift Counter

ABSORPTION LAW

4 BIT PARITY CHECKER

LOGIC GATES

Half Subtractor using NOR Gate

2 to 1 MUX using NOT gate

2 to 1 MUX using NOR gate

De Morgans laws

Single bit MC

BCD to Decimal Decoder

4 to 1 MUX

2 to 1 MUX

commutative property

ASSOCIATIVE PROPERTY

(A+B)(B+C)(C+A)=AB+BC+CA

4 BIT SYNCHRONOUS up COUNTER

Half adder

Full Adder

Full Adder using NAND Gate

Half Subtractor

Half Subtractor using NAND Gate

Full Subtractor

Full Subtractor using NOR Gate

HALF SUBTRACTOR

Full Adder using NOR Gate

2 bit MC

FULL ADDER

FULL ADDER

BCD to 7 segment Decoder

IMPLEMENT using MINTERMS with 16 to1 MUX

2 to 4 Decoder

1:8 DEMUX

24 to 1 MUX using 8 to 1 MUX

3 to 8 decoder

2 to 1 MUX using NAND gate

4 Bit BINARY to GRAY

Half Adder using NOR Gate

4 Bit BCD to Excess 3

3 BIT PARITY CHEKER

IMPLEMENTATION USING MINTEMS WITH 2 to1 MUX

8 TO 3 Priority ENCODER

4 to 2 priority encoder

Octal to Binary Encoder

32 to 1 MUX using to 1Mux

16 to 1 MUX

HALF ADDER