OR USING 2 TO 1 MUX

PIPO

SISO

sequence generator using counter

4 bit parity generator

3 bit Parity Checker

4 bit parity generator

2 bit Magnitude Comparator

3 bit Parity Checker

NOR USING 2 TO 1 MUX

ABSORPTION LAW (PART 2)

AND GATE

Untitled

Untitled

sequence generator using counter

Full Adder Using Basic Gates

8 TO 3 PRIORITY ENCODER

3 bit parity generator

BCD TO EXCESS-3

EXCESS-3 TO BCD

1 B

Serial In Serial Out Shift Register - D flip flop

FULL SUBTRACTOR USING BASIC GATES

1 bit Magnitude Comparator

4 bit parity checker

PISO

PIPO

implementation of full adder with mux and counter

4-bit Magnitude comparator

counter that counts 0,2,4,7,0

Full Subtractor using NAND gate

GRAY TO BINARY CODE CONVERTER

synchronous counter

BINARY TO GRAY CODE CONVERTER

Shift registers

mod-6 unit distance counter

3 bit even&odd parity generator

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MOD 6 Synchronous Up Counter

FULL ADDER

Figure 4.2 A serial binary adder

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

counter that counts 0,2,4,7,0

3 bit parity generator

4 BIT UNIVERSAL SHIFT REGISTER

Serial In Serial Out Shift Register - D flip flop

AND USING 2 TO 1 MUX

4-bit bidirectional shift register

MUX with counter

implementation of full adder with mux and counter

4 bit parity checker

Full Subtractor using NAND gate

implementation of full adder using counter

sequence generator using counter

SIPO

mod-6 unit distance counter

3 bit odd/even parity generator

PARALLEL ADDER CUM SUBTRACTOR

Full Adder using NOR Gate

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

Figure 4.2 A serial binary adder

4 bit bidirectional shift register