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8:1 MUX using Dual 4:1 MUX
8:1 MUX using Dual 4:1 MUXJK to D
JK to DLSB reduction
LSB reductionJK to SR
JK to SRVerification of D and T flipflop
Verification of D and T flipflopD to JK
D to JKT to JK
T to JKJK flipflop to D flipflop
JK flipflop to D flipflop2 - bit digital comparator
2 - bit digital comparatorEven and odd parity generator and checker
Even and odd parity generator and checkerBoolean representation using decoder
Boolean representation using decoderBoolean expression representation
Boolean expression representation16:1 MUX using 8:1 MUX
16:1 MUX using 8:1 MUXImplementation of (0,2,4,7,9,10,12,13,15) using 8:1 LSB
Implementation of (0,2,4,7,9,10,12,13,15) using 8:1 LSBUntitled
UntitledJK flipflop to T flipflop
JK flipflop to T flipflopEven and odd parity generator and checker
Even and odd parity generator and checker