Mahi Rana
Member since: 4 years
Educational Institution: Ajay Kumar Garg Engineering College
Country: India
Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.
Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.
Public
HA, FA, 4-Bit Adder, 8, 16... G to B, B to G, Decoder based on 1:2 Decoder..
HA, FA, 4-Bit Adder, 8, 16... G to B, B to G, Decoder based on 1:2 Decoder..
Public
Verify the excitation tables of various FLIP-FLOPS.
Verify the excitation tables of various FLIP-FLOPS.
Public
8-bit I/O system with 4-bit Internal register
8-bit I/O system with 4-bit Internal register
Public
Mahi Rana/ Design the data path of a computer from its register transfer language description.
Mahi Rana/ Design the data path of a computer from its register transfer language description.
Public
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