SOUNDARYA.S
Member since: 4 years
Educational Institution: Not Entered
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Half Adder
Half Adder
2 BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATOR
ENCDERS 1
ENCDERS 1
DFF using JKFF
DFF using JKFF
4 BIT RIPPLE COUNTER
4 BIT RIPPLE COUNTER
24 to 1 mux using 8 to 1 mux
24 to 1 mux using 8 to 1 mux
8 to 3 Priority Encoder
8 to 3 Priority Encoder
1 to 8 DEMUX
1 to 8 DEMUX
4 TO 1 MUX
4 TO 1 MUX
D FLIP FLOP USING SR FLIP FLOP
D FLIP FLOP USING SR FLIP FLOP
8 bit parity checker
8 bit parity checker
SHIFT COUNTER
SHIFT COUNTER
Full Adder
Full Adder
8-BIT MAGNITUDE COMPARATOR
8-BIT MAGNITUDE COMPARATOR
3 BIT PARITY GENETOR AND CHECKER
3 BIT PARITY GENETOR AND CHECKER
4-bit ripple carry adder/subtractor
4-bit ripple carry adder/subtractor
3 BIT PARITY GENERATOR
3 BIT PARITY GENERATOR
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL ADDER / SUBTRACTOR
3 BIT PARALLEL ADDER / SUBTRACTOR
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
decimal to bcd priority encoder
decimal to bcd priority encoder
BCD TO 7 SEGMENT DECODERS
BCD TO 7 SEGMENT DECODERS
T FLIP FLOP Using JK FLIP FLOP
T FLIP FLOP Using JK FLIP FLOP
TFF using SRFF
TFF using SRFF
TFF USING DFF
TFF USING DFF
SRFF USING TFF
SRFF USING TFF
SRFF using DFF
SRFF using DFF
TFF using JKFF
TFF using JKFF
SR FLIP FLOP USING T FLIP FLOP
SR FLIP FLOP USING T FLIP FLOP
SRFF using DFF
SRFF using DFF
JK FLIP FLOP USING SR FLIP FLOP
JK FLIP FLOP USING SR FLIP FLOP
4 bit ripple down counter
4 bit ripple down counter
JKFF using DFF
JKFF using DFF
MOD 12 COUNTER
MOD 12 COUNTER
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
SHIFT COUNTER
SHIFT COUNTER
MOD 7 COUNTER
MOD 7 COUNTER
PARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUT
32 to 1 mux using 4 to 1 mux
32 to 1 mux using 4 to 1 mux
IMPLEMENTATION OF MINTERMS USING 8 TO 1 MUX
IMPLEMENTATION OF MINTERMS USING 8 TO 1 MUX
3 bit Parity Checker
3 bit Parity Checker
4 bit ripple down counter
4 bit ripple down counter
1 to 16 demux
1 to 16 demux
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE UP/DOWN COUNTER
4 BIT RIPPLE UP/DOWN COUNTER
16 to 1 MUX
16 to 1 MUX
24 TO 1 MUX USING 1 MUX
24 TO 1 MUX USING 1 MUX
32 TO 1 MUX USING 4 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUX
3 to 8 Decoder
3 to 8 Decoder
2 to 4 Decoder
2 to 4 Decoder
8-BIT MAGNITUDE COMPARATOR
8-BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATOR
4 TO 1 MUX
4 TO 1 MUX
3 BIT PARITY GENERATOR AND CHECKER
3 BIT PARITY GENERATOR AND CHECKER
Untitled
Untitled
3 BIT PARITY GENERATOR AND CHECKER
3 BIT PARITY GENERATOR AND CHECKER
4 BIT PARITY GENERATOR
4 BIT PARITY GENERATOR
4-BIT PARITY GENERATOR
4-BIT PARITY GENERATOR
4 BIT PARITY CHECKER 4
4 BIT PARITY CHECKER 4
4 bit ripple down counter
4 bit ripple down counter
Adders
Adders
4 bit parity generator/checker
4 bit parity generator/checker
1-BIT MAGNITUDE COMPARATOR
1-BIT MAGNITUDE COMPARATOR
16 to 1 Mux
16 to 1 Mux
BCD to 7 Segment Decoder
BCD to 7 Segment Decoder
4 TO 1 MUX
4 TO 1 MUX
MOD 12 counter
MOD 12 counter
4 bit ripple down counter
4 bit ripple down counter
Half Adder
Half Adder
JK FLIP FLOP USING T FLIP FLOP
JK FLIP FLOP USING T FLIP FLOP
4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS
4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS
16 to 1 mux
16 to 1 mux
8 bit parity checker
8 bit parity checker
16 to 1 MUX
16 to 1 MUX
8 TO 1 MUX
8 TO 1 MUX
16 to 1 MUX
16 to 1 MUX
16 to 1 mux
16 to 1 mux
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
mod 12 counter
mod 12 counter
4 to 2 Priority Encoder
4 to 2 Priority Encoder
4 to 16 Line Decoder
4 to 16 Line Decoder
PARALLEL IN SERIAL OUT
PARALLEL IN SERIAL OUT
4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS
4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS
4 bit parity generator/checker
4 bit parity generator/checker
BCD to Decimal Decoder
BCD to Decimal Decoder
Half Adder
Half Adder
8 to 1 MUX
8 to 1 MUX
T FLIP FLOP Using SR FLIP FLOP
T FLIP FLOP Using SR FLIP FLOP
IMPLEMENTATION OF MINTERMS USING 4:1 MUX
IMPLEMENTATION OF MINTERMS USING 4:1 MUX
SR FLIP FLOP USING JK FLIP FLOP
SR FLIP FLOP USING JK FLIP FLOP
Shift Register - SISO Mode
Shift Register - SISO Mode
3 BIT PARALLEL ADDER / SUBTRACTOR
3 BIT PARALLEL ADDER / SUBTRACTOR
16 to 1 MUX
16 to 1 MUX
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
4 bit ripple down counter
4 bit ripple down counter
IMPLEMENTATION OF MINTERMS USING 4:1 MUX
IMPLEMENTATION OF MINTERMS USING 4:1 MUX
3 BIT PARITY GENERATOR
3 BIT PARITY GENERATOR
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
D FLIP FLOP using JK FLIP FLOP
D FLIP FLOP using JK FLIP FLOP
synchronous up/down counter
synchronous up/down counter
4 bit Parity Generator
4 bit Parity Generator
D FLIP FLOP Using T FLIP FLOP
D FLIP FLOP Using T FLIP FLOP
4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.
4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.
IMPLEMENTATION OF MINTERMS USING 8 TO 1 MUX
IMPLEMENTATION OF MINTERMS USING 8 TO 1 MUX
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