project.name

S.Tamil Eniyal

Member since: 4 years

Educational Institution: Not Entered

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1 TO 4 DEMUX

1 TO 4 DEMUX
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D FLIP FLOP USING SR FLIP FLOP

D FLIP FLOP USING SR FLIP FLOP
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JK FLIPFLOP

JK FLIPFLOP
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Half Adder

Half Adder
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SHIFT COUNTER

SHIFT COUNTER
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MOD 12 COUNTER

MOD 12 COUNTER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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FULL ADDER USING TWO HALF ADDERS

FULL ADDER USING TWO HALF ADDERS
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4 BIT MAGNITUDE COMPARATOR

4 BIT MAGNITUDE COMPARATOR
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MOD 7 COUNTER

MOD 7 COUNTER
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PARALLEL IN SERIAL OUT

PARALLEL IN SERIAL OUT
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4 bit ripple down counter

4 bit ripple down counter
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8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
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PARALLEL IN PARALLEL OUT

PARALLEL IN PARALLEL OUT
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CONSENSUS THEOREM

CONSENSUS THEOREM
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HALF ADDER

HALF ADDER
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Untitled

Untitled
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FULL ADDER

FULL ADDER
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synchronous up/down counter

synchronous up/down counter
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JK-FF using NAND Gates

JK-FF using NAND Gates
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2 TO 4 DECODER

2 TO 4 DECODER
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2 to 4 Decoder

2 to 4 Decoder
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T FLIP FLOP Using JK FLIP FLOP

T FLIP FLOP Using JK FLIP FLOP
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SRFF

SRFF
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D FLIP FLOP Using T FLIP FLOP

D FLIP FLOP Using T FLIP FLOP
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T FLIPFLOP

T FLIPFLOP
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SRFF

SRFF
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SR FLIP FLOP USING JK FLIP FLOP

SR FLIP FLOP USING JK FLIP FLOP
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SR FLIP FLOP USING D FLIP FLOP

SR FLIP FLOP USING D FLIP FLOP
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RING COUNTER

RING COUNTER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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FULL ADDER

FULL ADDER
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FULL ADDER

FULL ADDER
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ADDERS

ADDERS
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D FLIP FLOP using JK FLIP FLOP

D FLIP FLOP using JK FLIP FLOP
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4x2 Priority Encoder

4x2 Priority Encoder
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HALF SUBTRACTOR

HALF SUBTRACTOR
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2 to 1 MUX

2 to 1 MUX
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4 to 1 MUX

4 to 1 MUX
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8 to 1 MUX

8 to 1 MUX
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NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
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AND & OR gate

AND & OR gate
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NOT gate

NOT gate
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NAND & NOR date

NAND & NOR date
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EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
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Basic logic gates

Basic logic gates
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DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
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DeMorgan's theorem

DeMorgan's theorem
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2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
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3 BIT PARITY CHECKER

3 BIT PARITY CHECKER
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1 TO 16 DEMUX

1 TO 16 DEMUX
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OCTAL TO BINARY ENCODER

OCTAL TO BINARY ENCODER
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FULL ADDER

FULL ADDER
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3 TO 8 DECODER

3 TO 8 DECODER
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16 T0 1 MUX

16 T0 1 MUX
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HALF ADDER

HALF ADDER
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24 TO 1 MUX USING 8 TO 1 MUX

24 TO 1 MUX USING 8 TO 1 MUX
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32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX
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HALF ADDER

HALF ADDER
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HALF ADDER

HALF ADDER
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HALF SUBTRACTOR

HALF SUBTRACTOR
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HALF SUBTRACTOR

HALF SUBTRACTOR
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL ADDER

FULL ADDER
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FULL ADDER

FULL ADDER
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FULL ADDER

FULL ADDER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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HALF ADDER

HALF ADDER
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SRFF

SRFF
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D FLIPFLOP

D FLIPFLOP
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AND USING 2 TO 1 MUX

AND USING 2 TO 1 MUX
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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Associative property

Associative property
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ABSORPTION LAWS

ABSORPTION LAWS
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FULL ADDER

FULL ADDER
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HALF ADDER

HALF ADDER
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HALF ADDER

HALF ADDER
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FULL ADDER

FULL ADDER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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SERIAL IN SERIAL OUT

SERIAL IN SERIAL OUT
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4 TO 2 ENCODER

4 TO 2 ENCODER
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4 bit ripple down counter

4 bit ripple down counter
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Binary to gray code converter

Binary to gray code converter
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BCD TO 7 SEGMENT DECODERS

BCD TO 7 SEGMENT DECODERS
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SR FLIP FLOP USING T FLIP FLOP

SR FLIP FLOP USING T FLIP FLOP
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4 BIT RIPPLE COUNTER

4 BIT RIPPLE COUNTER
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4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
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FULL ADDER

FULL ADDER
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Untitled

Untitled
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Gray to binary code converter

Gray to binary code converter
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OR USING 2 TO 1 MUX

OR USING 2 TO 1 MUX
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JK FLIP FLOP USING T FLIP FLOP

JK FLIP FLOP USING T FLIP FLOP
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NAND Based SR FF

NAND Based SR FF
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FULL ADDER

FULL ADDER
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FULL ADDER

FULL ADDER
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BCD to excess-3 converter

BCD to excess-3 converter
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1 to 2 demux

1 to 2 demux
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2 TO 4 DECODER

2 TO 4 DECODER
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4 bit parity generator/checker

4 bit parity generator/checker
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T-FF using NAND Gates

T-FF using NAND Gates
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BCD ADDER

BCD ADDER
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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3 BIT PARITY GENERATOR

3 BIT PARITY GENERATOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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D-FF using NAND Gates

D-FF using NAND Gates
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1 BIT MAGNITUDE COMPARATOR

1 BIT MAGNITUDE COMPARATOR
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Excess-3 to BCD converter

Excess-3 to BCD converter
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4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.

4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.
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1 to 8 DEMUX

1 to 8 DEMUX
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BCD to excess-3 converter

BCD to excess-3 converter
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JK FLIP FLOP USING SR FLIP FLOP

JK FLIP FLOP USING SR FLIP FLOP
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ENCDERS 1

ENCDERS 1
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implementation of full adder using counter

implementation of full adder using counter
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2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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implementation of full adder using counter

implementation of full adder using counter
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4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS
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SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
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Verification of Booleanpostulates and laws

Verification of Booleanpostulates and laws
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Hlaf adder

Hlaf adder
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NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
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RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
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T FLIP FLOP Using SR FLIP FLOP

T FLIP FLOP Using SR FLIP FLOP
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