1 TO 4 DEMUX

D FLIP FLOP USING SR FLIP FLOP

JK FLIPFLOP

Half Adder

SHIFT COUNTER

MOD 12 COUNTER

FULL SUBTRACTOR

FULL ADDER USING TWO HALF ADDERS

4 BIT MAGNITUDE COMPARATOR

MOD 7 COUNTER

PARALLEL IN SERIAL OUT

4 bit ripple down counter

8 TO 3 PRIORITY ENCODER

PARALLEL IN PARALLEL OUT

CONSENSUS THEOREM

HALF ADDER

Untitled

FULL ADDER

synchronous up/down counter

JK-FF using NAND Gates

2 TO 4 DECODER

2 to 4 Decoder

T FLIP FLOP Using JK FLIP FLOP

SRFF

D FLIP FLOP Using T FLIP FLOP

T FLIPFLOP

SRFF

SR FLIP FLOP USING JK FLIP FLOP

SR FLIP FLOP USING D FLIP FLOP

RING COUNTER

FULL SUBTRACTOR

FULL ADDER

FULL ADDER

ADDERS

D FLIP FLOP using JK FLIP FLOP

4x2 Priority Encoder

HALF SUBTRACTOR

2 to 1 MUX

4 to 1 MUX

8 to 1 MUX

NAND USING 2 TO 1 MUX

AND & OR gate

NOT gate

NAND & NOR date

EXOR USING 2 TO 1 MUX

Basic logic gates

DISTRIBUTIVE LAW

DeMorgan's theorem

2 BIT MAGNITUDE COMPARATOR

3 BIT PARITY CHECKER

1 TO 16 DEMUX

OCTAL TO BINARY ENCODER

FULL ADDER

3 TO 8 DECODER

16 T0 1 MUX

HALF ADDER

24 TO 1 MUX USING 8 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX

HALF ADDER

HALF ADDER

HALF SUBTRACTOR

HALF SUBTRACTOR

HALF SUBTRACTOR

FULL ADDER

FULL ADDER

FULL ADDER

FULL SUBTRACTOR

FULL SUBTRACTOR

HALF ADDER

SRFF

D FLIPFLOP

AND USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX

Associative property

ABSORPTION LAWS

FULL ADDER

HALF ADDER

FULL ADDER

FULL SUBTRACTOR

SERIAL IN SERIAL OUT

4 TO 2 ENCODER

4 bit ripple down counter

Binary to gray code converter

BCD TO 7 SEGMENT DECODERS

SR FLIP FLOP USING T FLIP FLOP

4 BIT RIPPLE COUNTER

4 BIT UP-DOWN COUNTER

FULL ADDER

Untitled

Gray to binary code converter

OR USING 2 TO 1 MUX

JK FLIP FLOP USING T FLIP FLOP

NAND Based SR FF

FULL ADDER

BCD to excess-3 converter

1 to 2 demux

2 TO 4 DECODER

4 bit parity generator/checker

T-FF using NAND Gates

BCD ADDER

implementation of full adder with mux and counter

DECIMAL TO BCD ENCODER

FULL SUBTRACTOR

3 BIT PARITY GENERATOR

FULL SUBTRACTOR

D-FF using NAND Gates

1 BIT MAGNITUDE COMPARATOR

Excess-3 to BCD converter

1 to 8 DEMUX

BCD to excess-3 converter

JK FLIP FLOP USING SR FLIP FLOP

ENCDERS 1

implementation of full adder using counter

2 BIT MAGNITUDE COMPARATOR

FULL SUBTRACTOR

implementation of full adder using counter

SERIAL IN PARALLEL OUT

Verification of Booleanpostulates and laws

Hlaf adder

NOT USING 2 TO 1 MUX

HALF ADDER

RIPPLE CARRY SUBTRACTOR

FULL ADDER

T FLIP FLOP Using SR FLIP FLOP

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS

4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.