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1 TO 4 DEMUX
1 TO 4 DEMUXD FLIP FLOP USING SR FLIP FLOP
D FLIP FLOP USING SR FLIP FLOPJK FLIPFLOP
JK FLIPFLOPHalf Adder
Half AdderSHIFT COUNTER
SHIFT COUNTERMOD 12 COUNTER
MOD 12 COUNTERFULL SUBTRACTOR
FULL SUBTRACTORFULL ADDER USING TWO HALF ADDERS
FULL ADDER USING TWO HALF ADDERS4 BIT MAGNITUDE COMPARATOR
4 BIT MAGNITUDE COMPARATORMOD 7 COUNTER
MOD 7 COUNTERPARALLEL IN SERIAL OUT
PARALLEL IN SERIAL OUT4 bit ripple down counter
4 bit ripple down counter8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODERPARALLEL IN PARALLEL OUT
PARALLEL IN PARALLEL OUTCONSENSUS THEOREM
CONSENSUS THEOREMHALF ADDER
HALF ADDERUntitled
UntitledFULL ADDER
FULL ADDERsynchronous up/down counter
synchronous up/down counterJK-FF using NAND Gates
JK-FF using NAND Gates2 TO 4 DECODER
2 TO 4 DECODER2 to 4 Decoder
2 to 4 DecoderT FLIP FLOP Using JK FLIP FLOP
T FLIP FLOP Using JK FLIP FLOPSRFF
SRFFD FLIP FLOP Using T FLIP FLOP
D FLIP FLOP Using T FLIP FLOPT FLIPFLOP
T FLIPFLOPSRFF
SRFFSR FLIP FLOP USING JK FLIP FLOP
SR FLIP FLOP USING JK FLIP FLOPSR FLIP FLOP USING D FLIP FLOP
SR FLIP FLOP USING D FLIP FLOPRING COUNTER
RING COUNTERFULL SUBTRACTOR
FULL SUBTRACTORFULL ADDER
FULL ADDERFULL ADDER
FULL ADDERADDERS
ADDERSD FLIP FLOP using JK FLIP FLOP
D FLIP FLOP using JK FLIP FLOP4x2 Priority Encoder
4x2 Priority EncoderHALF SUBTRACTOR
HALF SUBTRACTOR2 to 1 MUX
2 to 1 MUX4 to 1 MUX
4 to 1 MUX8 to 1 MUX
8 to 1 MUXNAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUXAND & OR gate
AND & OR gateNOT gate
NOT gateNAND & NOR date
NAND & NOR dateEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUXBasic logic gates
Basic logic gatesDISTRIBUTIVE LAW
DISTRIBUTIVE LAWDeMorgan's theorem
DeMorgan's theorem2 BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATOR3 BIT PARITY CHECKER
3 BIT PARITY CHECKER1 TO 16 DEMUX
1 TO 16 DEMUXOCTAL TO BINARY ENCODER
OCTAL TO BINARY ENCODERFULL ADDER
FULL ADDER3 TO 8 DECODER
3 TO 8 DECODER16 T0 1 MUX
16 T0 1 MUXHALF ADDER
HALF ADDER24 TO 1 MUX USING 8 TO 1 MUX
24 TO 1 MUX USING 8 TO 1 MUX32 TO 1 MUX USING 4 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUXHALF ADDER
HALF ADDERHALF ADDER
HALF ADDERHALF SUBTRACTOR
HALF SUBTRACTORHALF SUBTRACTOR
HALF SUBTRACTORHALF SUBTRACTOR
HALF SUBTRACTORFULL ADDER
FULL ADDERFULL ADDER
FULL ADDERFULL ADDER
FULL ADDERFULL SUBTRACTOR
FULL SUBTRACTORFULL SUBTRACTOR
FULL SUBTRACTORHALF ADDER
HALF ADDERSRFF
SRFFD FLIPFLOP
D FLIPFLOPAND USING 2 TO 1 MUX
AND USING 2 TO 1 MUXNOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUXAssociative property
Associative propertyABSORPTION LAWS
ABSORPTION LAWSFULL ADDER
FULL ADDERHALF ADDER
HALF ADDERFULL ADDER
FULL ADDERFULL SUBTRACTOR
FULL SUBTRACTORSERIAL IN SERIAL OUT
SERIAL IN SERIAL OUT4 TO 2 ENCODER
4 TO 2 ENCODER4 bit ripple down counter
4 bit ripple down counterBinary to gray code converter
Binary to gray code converterBCD TO 7 SEGMENT DECODERS
BCD TO 7 SEGMENT DECODERSSR FLIP FLOP USING T FLIP FLOP
SR FLIP FLOP USING T FLIP FLOP4 BIT RIPPLE COUNTER
4 BIT RIPPLE COUNTER4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTERFULL ADDER
FULL ADDERUntitled
UntitledGray to binary code converter
Gray to binary code converterOR USING 2 TO 1 MUX
OR USING 2 TO 1 MUXJK FLIP FLOP USING T FLIP FLOP
JK FLIP FLOP USING T FLIP FLOPNAND Based SR FF
NAND Based SR FFFULL ADDER
FULL ADDERFULL ADDER
FULL ADDERBCD to excess-3 converter
BCD to excess-3 converter1 to 2 demux
1 to 2 demux2 TO 4 DECODER
2 TO 4 DECODER4 bit parity generator/checker
4 bit parity generator/checkerT-FF using NAND Gates
T-FF using NAND GatesBCD ADDER
BCD ADDERimplementation of full adder with mux and counter
implementation of full adder with mux and counterDECIMAL TO BCD ENCODER
DECIMAL TO BCD ENCODERFULL SUBTRACTOR
FULL SUBTRACTOR3 BIT PARITY GENERATOR
3 BIT PARITY GENERATORFULL SUBTRACTOR
FULL SUBTRACTORD-FF using NAND Gates
D-FF using NAND Gates1 BIT MAGNITUDE COMPARATOR
1 BIT MAGNITUDE COMPARATORExcess-3 to BCD converter
Excess-3 to BCD converter4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.
4 to 16 decoder with manual input | Décodeur 4 vers 16 avec entrées manuelles.1 to 8 DEMUX
1 to 8 DEMUXBCD to excess-3 converter
BCD to excess-3 converterJK FLIP FLOP USING SR FLIP FLOP
JK FLIP FLOP USING SR FLIP FLOPENCDERS 1
ENCDERS 1implementation of full adder using counter
implementation of full adder using counter2 BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATORFULL SUBTRACTOR
FULL SUBTRACTORimplementation of full adder using counter
implementation of full adder using counterSERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUTVerification of Booleanpostulates and laws
Verification of Booleanpostulates and lawsHlaf adder
Hlaf adderNOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUXHALF ADDER
HALF ADDERRIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTORT FLIP FLOP Using SR FLIP FLOP
T FLIP FLOP Using SR FLIP FLOP4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS
4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS