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BCD ADDER
BCD ADDERNAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOPTFF
TFFDFF USING JKFF
DFF USING JKFFTFF USING JKFF
TFF USING JKFFJK FLIPFLOP
JK FLIPFLOPT FLIPFLOP
T FLIPFLOP4 bit ripple counter
4 bit ripple counterMOD 12 COUNTER
MOD 12 COUNTERJK FLIPFLOP
JK FLIPFLOPSR FLIPFLOP
SR FLIPFLOP4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputsTFF USING SRFF
TFF USING SRFFRipple carry Adder
Ripple carry Addermod-6 unit distance counter
mod-6 unit distance counter4 bit bidirectional shift register
4 bit bidirectional shift register4 bit synchronous counter
4 bit synchronous counterPISO
PISO4 BIT SYNCHRONOUS UP COUNTER
4 BIT SYNCHRONOUS UP COUNTERNOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUXRipple carry Adder
Ripple carry Adder3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIERD Flipflop
D Flipflop3 BIT MAGNITUDE COMPARATOR
3 BIT MAGNITUDE COMPARATORimplementation of full adder with mux and counter
implementation of full adder with mux and counterJKFF USING DFF
JKFF USING DFFTFF USING DFF
TFF USING DFF4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN counterDecimal to BCD Encoder
Decimal to BCD Encoder4 bit adder/subtractor
4 bit adder/subtractorcircuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 08 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER4-bit ripple carry adder/subtractor
4-bit ripple carry adder/subtractor32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUXSRFF USING TFF
SRFF USING TFFJKFF using SRFF
JKFF using SRFFJKFF Using TFF
JKFF Using TFFDFF USING SRFF
DFF USING SRFFSRFF using DFF
SRFF using DFFD FLIPFLOP
D FLIPFLOPDFF USING TFF
DFF USING TFFDFF USING JKFF
DFF USING JKFFMOD 7 COUNTER
MOD 7 COUNTERSR FLIPFLOP
SR FLIPFLOP4 bit ripple down counter
4 bit ripple down counterSRFF USING JKFF
SRFF USING JKFF4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTERimplementation of full adder using counter
implementation of full adder using counter4 bit synchronous down counter
4 bit synchronous down counter3 bit binary counter
3 bit binary countercounter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0sequence generator using counter
sequence generator using counter4 bit synchronous counter
4 bit synchronous countercounter having the states 0-2--4-7-0
counter having the states 0-2--4-7-0PIPO
PIPOSIPO
SIPOSISO
SISORIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTORshift counter
shift counterring counter
ring counterIMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)16 to 1 mux
16 to 1 muxBCD to Decimal Decoder
BCD to Decimal DecoderBCD to 7 segment decoder
BCD to 7 segment decoderEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX8 to 1 MUX
8 to 1 MUX24 to 1 MUX using 8 to 1 MUX
24 to 1 MUX using 8 to 1 MUX2 to 1 MUX
2 to 1 MUXNOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX2 x 1 ENCODER
2 x 1 ENCODERIMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)4 x 2 ENCODER
4 x 2 ENCODER4 TO 16
4 TO 164 to 2 priority encoder
4 to 2 priority encoder3 x 8 DECODER
3 x 8 DECODER1 x 2 DECODER
1 x 2 DECODER1 to 2 DEMUX
1 to 2 DEMUX1 to 16 DEMUX
1 to 16 DEMUX2 TO 4 decoder
2 TO 4 decoderIMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)MUX with counter
MUX with counterIMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)2 x 4 DECODER
2 x 4 DECODEROctal to Binary Encoder
Octal to Binary EncoderNAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUXOR USING 2 TO 1 MUX
OR USING 2 TO 1 MUXNOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX4 to 1 MUX
4 to 1 MUXAND USING 2 TO 1 MUX
AND USING 2 TO 1 MUXIMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)1 to 8 DEMUX
1 to 8 DEMUX1 to 4 DEMUX
1 to 4 DEMUX2 to 4 Decoder
2 to 4 DecoderRIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR3 bit synchronous up/down counter
3 bit synchronous up/down counter4-bit ripple carry adder/subtractor
4-bit ripple carry adder/subtractorcircuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTERIMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)4 bit synchronous counter with ripple carry
4 bit synchronous counter with ripple carry