NOR USING 2 TO 1 MUX

MOD 12 COUNTER

TFF USING JKFF

BCD ADDER2

3- BIT PARITY GENERATOR

4-BIT PARITY GENERATOR

4-BIT PARITY CHECKER

2 BIT MAGNITUDE COMPARATOR

3 BIT MAGNITUDE COMPARATOR

FULL ADDER

8 TO 3 ENCODER

FULL ADDER

IMPLEMENTATION USING MUX(1)

3 x 8 DECODER

3 BIT MAGNITUDE COMPARATOR

JKFF Using TFF

TFF USING DFF

PIPO

SRFF USING TFF

SRFF using DFF

DFF USING SRFF

DFF USING JKFF

JKFF using SRFF

JKFF USING DFF

DFF USING TFF

TFF

JK FLIPFLOP

SR FLIPFLOP

D FLIPFLOP

SRFF USING JKFF

TFF USING SRFF

4 bit ripple counter

shift counter

ring counter

3 bit synchronous up/down counter

SISO

PISO

4 bit bidirectional shift register

4 BIT UNIVERSAL SHIFT REGISTER

SIPO

sequence generator using counter

counter that counts 0,2,4,7,0

counter having the states 0-2--4-7-0

FULL ADDER

BCD ADDER

mod-6 unit distance counter

jkflipflop

4-bit ripple carry adder/subtractor

1 to 2 DEMUX

1 to 8 DEMUX

1 to 4 DEMUX

1 to 16 DEMUX

24 to 1 MUX using 8 to 1 MUX

IMPLEMENTION USING MUX(2)

2 x 1 ENCODER

NOR USING 2 TO 1 MUX

Decimal to BCD Encoder

4 x 2 ENCODER

Octal to Binary Encoder

NOT USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX

2 x 4 DECODER

8 TO 3 PRIORITY ENCODER

BCD to 7 segment decoder

4 to 2 priority encoder

1 to 4 DEMUX

4 TO 16

1 to 2 DEMUX

IMPLEMENTION USING MUX(2)

IMPLEMENTATION USING MUX(1)

2 to 4 Decoder

2 TO 4 decoder

1-BIT MAGNITUDE COMPARATOR

4 to 1 MUX

2 to 1 MUX

16 to 1 mux

4 BIT MAGNITUDE COMPARATOR

OR USING 2 TO 1 MUX

AND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX

BCD to Decimal Decoder

IMPLEMENTATION USING MUX(1)

1 x 2 DECODER

8 to 1 MUX

3 BIT PARALLEL MULTIPLIER

32 to 1 MUX using 4 to 1 MUX