project.name

M.Kirthika

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

8 : 1 MUX

8 : 1 MUX
Public
project.name

MOD 12 COUNTER

MOD 12 COUNTER
Public
project.name

T FLIP FLOP USING JK FLIP FLOP

T FLIP FLOP USING JK FLIP FLOP
Public
project.name

XS 3 TO BCD CODE CONVERTER

XS 3 TO BCD CODE CONVERTER
Public
project.name

BCD TO DECIMAL DECODER

BCD TO DECIMAL DECODER
Public
project.name

8 TO 1 MUX

8 TO 1 MUX
Public
project.name

4 bit magnitude comparator

4 bit magnitude comparator
Public
project.name

OCTAL TO BINARY ENCODER

OCTAL TO BINARY ENCODER
Public
project.name

UP / DOWN COUNTER

UP / DOWN COUNTER
Public
project.name

D FLIPFLOP USING JK FLIPFLOP

D FLIPFLOP USING JK FLIPFLOP
Public
project.name

RING COUNTER

RING COUNTER
Public
project.name

T FLIP FLOP USING D FLIP FLOP

T FLIP FLOP USING D FLIP FLOP
Public
project.name

BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
Public
project.name

RIPPLE CARRY ADDER

RIPPLE CARRY ADDER
Public
project.name

1 BIT MAGNITUDE COMPARATOR

1 BIT MAGNITUDE COMPARATOR
Public
project.name

3 BIT MAGNITUDE COMPARATOR

3 BIT MAGNITUDE COMPARATOR
Public
project.name

1. Basic Gates

1. Basic Gates
Public
project.name

Untitled

Untitled
Public
project.name

1 TO 2 DEMUX

1 TO 2 DEMUX
Public
project.name

DECIMAL TO BCD PRIORITY ENCOUNTER

DECIMAL TO BCD PRIORITY ENCOUNTER
Public
project.name

Practical 2

Practical 2
Public
project.name

FULL ADDER

FULL ADDER
Public
project.name

SR FLIP FLOP USING LOGIC GATES

SR FLIP FLOP USING LOGIC GATES
Public
project.name

PARALLEL IN PARALLEL OUT

PARALLEL IN PARALLEL OUT
Public
project.name

SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
Public
project.name

PARALLEL IN SERIAL OUT

PARALLEL IN SERIAL OUT
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

3 bit even / odd parity generator

3 bit even / odd parity generator
Public
project.name

DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
Public
project.name

3 BIT ODD/EVEN PARITY CHECKERS

3 BIT ODD/EVEN PARITY CHECKERS
Public
project.name

HALF SUBSTRACTOR

HALF SUBSTRACTOR
Public
project.name

Binary to gray code converter

Binary to gray code converter
Public
project.name

4 TO 1 MUX

4 TO 1 MUX
Public
project.name

SEERIAL IN SERIAL OUT

SEERIAL IN SERIAL OUT
Public
project.name

4 BIT ADDER

4 BIT ADDER
Public
project.name

1 TO 4 DEMUX

1 TO 4 DEMUX
Public
project.name

BCD to Excess-3 Converter

BCD to Excess-3 Converter
Public
project.name

FULL ADDER

FULL ADDER
Public
project.name

2 bit magnitude comparator

2 bit magnitude comparator
Public
project.name

1.Basic Gates

1.Basic Gates
Public
project.name

Decimal to BCD priority Encoder

Decimal to BCD priority Encoder
Public
project.name

JK FLIP FLOP USING SR FLIP FLOP

JK FLIP FLOP USING SR FLIP FLOP
Public
project.name

Untitled

Untitled
Public
project.name

T FLIP FLOP USING SR FLIP FLOP

T FLIP FLOP USING SR FLIP FLOP
Public
project.name

ADDERS AND SUBTRACTORS USING BASIC AND UNIVERSAL GATES

ADDERS AND SUBTRACTORS USING BASIC AND UNIVERSAL GATES
Public
project.name

RIPPLE COUNTER

RIPPLE COUNTER
Public
project.name

BCD ADDER

BCD ADDER
Public
project.name

1 TO 8 DEMUX

1 TO 8 DEMUX
Public
project.name

FULL SUBTRACTOR

FULL SUBTRACTOR
Public
project.name

4 TO 1 MUX

4 TO 1 MUX
Public
project.name

BOOLEAN POSTULATS AND LAWS

BOOLEAN POSTULATS AND LAWS
Public
project.name

JK FLIPFLOP USING D FLIP FLOP

JK FLIPFLOP USING D FLIP FLOP
Public
project.name

16 TO 1 MUX

16 TO 1 MUX
Public
project.name

D FLIP FLOP USING SR FLIP FLOP

D FLIP FLOP USING SR FLIP FLOP
Public
project.name

SHIFT COUNTER

SHIFT COUNTER
Public
project.name

9 BIT ODD / EVEN PARITY CHECKERS

9 BIT ODD / EVEN PARITY CHECKERS
Public
project.name

Untitled

Untitled
Public
project.name

1 BIT MAGNITUDE COMPARATOR

1 BIT MAGNITUDE COMPARATOR
Public
project.name

BOOLEAN THEOREMS USING LOGIC GATES

BOOLEAN THEOREMS USING LOGIC GATES
Public
project.name

MOD 10 COUNTER

MOD 10 COUNTER
Public
project.name

2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
Public
project.name

HALF ADDER USING LOGIC GATES

HALF ADDER USING LOGIC GATES
Public
project.name

1 TO 4 DEMUX

1 TO 4 DEMUX
Public
project.name
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M.Kirthika is not a collaborator of any project.