project.name

Lackhmi priya G

Member since: 249 days

Educational Institution: Not Entered

Country: Not Entered

ABSORPTION LAW

ABSORPTION LAW
Public
ABSORPTION LAW

Untitled

Untitled
Public
Untitled

FULL SUBSTRACTOR USING NOR GATE

FULL SUBSTRACTOR USING NOR GATE
Public
FULL SUBSTRACTOR USING NOR GATE

SYNCHRONOUS UP DOWN CIRCUIT

SYNCHRONOUS UP DOWN CIRCUIT
Public
SYNCHRONOUS UP DOWN CIRCUIT

NOT 2X1 MUX

NOT 2X1 MUX
Public
NOT 2X1 MUX

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
Public
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX

DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
Public
DECIMAL TO BCD ENCODER

2 BIT MADNITUDE COMPARATOR

2 BIT MADNITUDE COMPARATOR
Public
2 BIT MADNITUDE COMPARATOR

question 6

question 6
Public
question 6

Untitled

Untitled
Public
Untitled

OR GATE

OR GATE
Public
OR GATE

3 BIT PARITY GENERATOR

3 BIT PARITY GENERATOR
Public
3 BIT PARITY GENERATOR

8 X 3 OCTAL TO BINARY ENCODER

8 X 3 OCTAL TO BINARY ENCODER
Public
8 X 3 OCTAL TO BINARY ENCODER

asynchronous 4 bit ripple counter with decoded output

asynchronous 4 bit ripple counter with decoded output
Public
asynchronous 4 bit ripple counter with decoded output

4 BIT RIPPLE UP/DOWN COUNTER

4 BIT RIPPLE UP/DOWN COUNTER
Public
4 BIT RIPPLE UP/DOWN COUNTER

MOD 12 COUNTER

MOD 12 COUNTER
Public
MOD 12 COUNTER

SYNCHRONOUS UP/DOWN COUNTER

SYNCHRONOUS UP/DOWN COUNTER
Public
SYNCHRONOUS UP/DOWN COUNTER

mod 10 counter

mod 10 counter
Public
mod 10 counter

SYNCHRONOUS UP COUNTER

SYNCHRONOUS UP COUNTER
Public
SYNCHRONOUS UP COUNTER

Circuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0

Circuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0
Public
Circuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0

SERIAL IN PARALLEL OUT SHIFT REGISTER

SERIAL IN PARALLEL OUT SHIFT REGISTER
Public
SERIAL IN PARALLEL OUT SHIFT REGISTER

UNIVERSAL SHIFT COUNTER

UNIVERSAL SHIFT COUNTER
Public
UNIVERSAL SHIFT COUNTER

NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
Public
NAND BASED SR  FLIPFLOP

JK FLIPFLOP USING INBUILT

JK FLIPFLOP USING INBUILT
Public
JK FLIPFLOP USING INBUILT

2.DIFF USING JKFF

2.DIFF USING JKFF
Public
2.DIFF USING JKFF

9. SRFF USING DFF

9. SRFF USING DFF
Public
9. SRFF USING DFF

DELAY FLIPFLOP USING INBUILT

DELAY FLIPFLOP USING INBUILT
Public
DELAY FLIPFLOP USING INBUILT

8. SRFF USING TFF

8. SRFF USING TFF
Public
8. SRFF USING TFF

4.TFF USING SRFF

4.TFF USING SRFF
Public
4.TFF USING SRFF

11. JKFF USING DFF

11. JKFF USING DFF
Public
11. JKFF USING DFF

10. JKK USING SRFF

10. JKK USING SRFF
Public
10. JKK USING SRFF

8. SRFF USING TFF

8. SRFF USING TFF
Public
8. SRFF USING TFF

BCD ADDER USING IC7483

BCD ADDER USING IC7483
Public
BCD ADDER USING IC7483

BCD ADDER

BCD ADDER
Public
BCD ADDER

BCD ADDER

BCD ADDER
Public
BCD ADDER

2X1 MUX

2X1 MUX
Public
2X1 MUX

COMMUTATIVE LAW

COMMUTATIVE LAW
Public
COMMUTATIVE LAW

NAND 2X1 MUX

NAND 2X1 MUX
Public
NAND 2X1 MUX

EXCESS TO BCD CONVERTER

EXCESS TO BCD CONVERTER
Public
EXCESS TO BCD CONVERTER

UNIVERSAL SHIFT COUNTER

UNIVERSAL SHIFT COUNTER
Public
UNIVERSAL SHIFT COUNTER

24 X 1 MUX USING 8 X 1 MUX

24 X 1 MUX USING 8 X 1 MUX
Public
24 X 1 MUX USING 8 X 1 MUX

1 X 2 DEMUX

1 X 2 DEMUX
Public
1 X 2 DEMUX

NOR GATE

NOR GATE
Public
NOR GATE

Boolean Laws Of Addition

Boolean Laws Of Addition
Public
Boolean Laws Of Addition

BOOLEAN LAWS OF MULTIPLICATION

BOOLEAN LAWS OF MULTIPLICATION
Public
BOOLEAN LAWS OF MULTIPLICATION

XNOR GATE

XNOR GATE
Public
XNOR GATE

NOT GATE

NOT GATE
Public
NOT GATE

HALF SUBTRACTOR USING XOR GATE

HALF SUBTRACTOR USING XOR GATE
Public
HALF SUBTRACTOR USING XOR GATE

ASSOCIATIVE LAW

ASSOCIATIVE LAW
Public
ASSOCIATIVE LAW

4 TO 2 ENCODER

4 TO 2 ENCODER
Public
4 TO 2 ENCODER

HALF SUBTRACTOR USING BASIC GATES

HALF SUBTRACTOR USING BASIC GATES
Public
HALF SUBTRACTOR USING BASIC GATES

USING 4 X 1 MUX

USING 4 X 1 MUX
Public
USING 4 X 1 MUX

HALF ADDER USING NOR GATES

HALF ADDER USING NOR GATES
Public
HALF ADDER USING NOR GATES

HALF ADDER USING XOR GATE

HALF ADDER USING XOR GATE
Public
HALF ADDER USING XOR GATE

3 BIT PARITY CHECKER

3 BIT PARITY CHECKER
Public
3 BIT PARITY CHECKER

BCD TO EXCESS-3 CONVERTER

BCD TO EXCESS-3 CONVERTER
Public
BCD TO EXCESS-3 CONVERTER

Untitled

Untitled
Public
Untitled

HALF ADDER USING BASIC GATES

HALF ADDER USING BASIC GATES
Public
HALF ADDER USING BASIC GATES

FULL SUBSTRACTOR USING USING BASIC GATES

FULL SUBSTRACTOR USING USING BASIC GATES
Public
FULL SUBSTRACTOR USING USING BASIC GATES

EXOR 2X1 MUX

EXOR 2X1 MUX
Public
EXOR 2X1 MUX

3 TO 8 DECODER

3 TO 8 DECODER
Public
3 TO 8 DECODER

HALF SUBTRACTOR USING NAND GATE

HALF SUBTRACTOR USING NAND GATE
Public
HALF SUBTRACTOR USING NAND GATE

4 TO 1 MUX

4 TO 1 MUX
Public
4 TO 1 MUX

FULL ADDER USING XOR GATE

FULL ADDER USING XOR GATE
Public
FULL ADDER USING XOR GATE

4 BIT PARITY GENERATOR

4 BIT PARITY GENERATOR
Public
4 BIT PARITY GENERATOR

4 BIT PARITY CHECKER

4 BIT PARITY CHECKER
Public
4 BIT PARITY CHECKER

OR 2 TO 1 MUX

OR 2 TO 1 MUX
Public
OR 2 TO 1 MUX

AND 2 TO 1 MUX

AND 2 TO 1 MUX
Public
AND 2 TO 1 MUX

USING 8 X 1 MUX

USING 8 X 1 MUX
Public
USING 8 X 1 MUX

FULL SUBTRACTOR USING XOR GATE

FULL SUBTRACTOR USING XOR GATE
Public
FULL SUBTRACTOR USING XOR GATE

FULL ADDER USING NOR GATES

FULL ADDER USING NOR GATES
Public
FULL ADDER USING NOR GATES

HALF ADDER USING NAND GATES

HALF ADDER USING NAND GATES
Public
HALF ADDER USING NAND GATES

FULL ADDER USING NAND GATE

FULL ADDER USING NAND GATE
Public
FULL ADDER USING NAND GATE

HALF SUBTRACTOR USING NOR GATE

HALF SUBTRACTOR USING NOR GATE
Public
HALF SUBTRACTOR USING NOR GATE

1 TO 2 DECODER

1 TO 2 DECODER
Public
1 TO 2 DECODER

1 BIT MAGNITUDE COMPARATOR

1 BIT MAGNITUDE COMPARATOR
Public
1 BIT MAGNITUDE COMPARATOR

BCD TO EXCESS -3 CONVERTER

BCD TO EXCESS -3 CONVERTER
Public
BCD TO EXCESS -3 CONVERTER

SHIFT COUNTER

SHIFT COUNTER
Public
SHIFT COUNTER

DONT KNOW

DONT KNOW
Public
DONT KNOW

Asynchronous 4 bit ripple down counter

Asynchronous 4 bit ripple down counter
Public
Asynchronous 4 bit ripple down counter

ASYNCHRONOUS 4 BIT RIPPLE COUNTER

ASYNCHRONOUS 4 BIT RIPPLE COUNTER
Public
ASYNCHRONOUS 4 BIT RIPPLE COUNTER

MOD 7 COUNTER

MOD 7 COUNTER
Public
MOD 7 COUNTER

MOD 7 COUNTER

MOD 7 COUNTER
Public
MOD 7 COUNTER

SYNCHRONOUS GENERATOR USING COUNTER

SYNCHRONOUS GENERATOR USING COUNTER
Public
SYNCHRONOUS GENERATOR USING COUNTER

SERIAL IN SERIAL OUT SHIFT REGISTER

SERIAL IN SERIAL OUT SHIFT REGISTER
Public
SERIAL IN SERIAL OUT SHIFT REGISTER

PARALLEL IN PARALLEL OUT SHIFT REGISTER

PARALLEL IN PARALLEL OUT SHIFT REGISTER
Public
PARALLEL IN PARALLEL OUT SHIFT REGISTER

NOR 2X1 MUX

NOR 2X1 MUX
Public
NOR 2X1 MUX

1 X 4 MUX

1 X 4 MUX
Public
1 X 4 MUX

SR FLIPFLOP USING INBUILT

SR FLIPFLOP USING INBUILT
Public
SR FLIPFLOP USING INBUILT

JK FLIPFLOP USING INBUILT

JK FLIPFLOP USING INBUILT
Public
JK FLIPFLOP USING INBUILT

T FLIPFLOP USING INBUILT

T FLIPFLOP USING INBUILT
Public
T FLIPFLOP USING INBUILT

1. DIFF USING SRFF

1. DIFF USING SRFF
Public
1. DIFF USING SRFF

6. TFF USING DFF

6. TFF USING DFF
Public
6. TFF USING DFF

DEMORGANS LAW

DEMORGANS LAW
Public
DEMORGANS LAW

4 X 2 PRIORITY ENCODER

4 X 2 PRIORITY ENCODER
Public
4 X 2 PRIORITY ENCODER

2 X 1 ENCODER

2 X 1 ENCODER
Public
2 X 1 ENCODER

AND GATE

AND GATE
Public
AND GATE

FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
Public
FULL ADDER USING BASIC GATES

2 TO 4 DECODER

2 TO 4 DECODER
Public
2 TO 4 DECODER

BCD ADDER 1

BCD ADDER 1
Public
BCD ADDER 1

QUESTION 7

QUESTION 7
Public
QUESTION 7

INCOMPLETE

INCOMPLETE
Public
INCOMPLETE

4 bit full adder 1

4 bit full adder 1
Public
4 bit full adder 1

SYNCHRONOUS DOWN COUNTER

SYNCHRONOUS DOWN COUNTER
Public
SYNCHRONOUS DOWN COUNTER

xor gate

xor gate
Public
xor gate

4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER

4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER
Public
4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUT

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUT
Public
4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUT

MOD 12 COUNTER

MOD 12 COUNTER
Public
MOD 12 COUNTER

SHIFT COUNTER

SHIFT COUNTER
Public
SHIFT COUNTER

mod 12 counter

mod 12 counter
Public
mod 12 counter

RING COUNTER

RING COUNTER
Public
RING COUNTER

SYNCHRONOUS DOWN COUNTER

SYNCHRONOUS DOWN COUNTER
Public
SYNCHRONOUS DOWN COUNTER

GRAY TO BINARY CODE CONVERTER

GRAY TO BINARY CODE CONVERTER
Public
GRAY TO BINARY CODE CONVERTER

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
NOR BASED SR  FLIPFLOP

D FLIPFLOP USING LOGIC GATE

D FLIPFLOP USING LOGIC GATE
Public
D FLIPFLOP USING LOGIC GATE

JACK KILBY FLIPFLOP USING LOGICGATES

JACK KILBY FLIPFLOP USING LOGICGATES
Public
JACK KILBY FLIPFLOP USING LOGICGATES

T FLIPFLOP USING LOGIC GATES

T FLIPFLOP USING LOGIC GATES
Public
T FLIPFLOP USING LOGIC GATES

BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
Public
BCD TO 7 SEGMENT DECODER

USING 16 X 1 MUX

USING 16 X 1 MUX
Public
USING 16 X 1 MUX

8 X 3 OCTAL TO BINARY ENCODER

8 X 3 OCTAL TO BINARY ENCODER
Public
8 X 3 OCTAL TO BINARY ENCODER

7. SRFF USING JKFF

7. SRFF USING JKFF
Public
7. SRFF USING JKFF

5. TFF USING JKFF

5. TFF USING JKFF
Public
5. TFF USING JKFF

3.DFF USING TFF

3.DFF USING TFF
Public
3.DFF USING TFF

12. JK FF USING TFF

12. JK FF USING TFF
Public
12. JK FF USING TFF

RING COUNTER

RING COUNTER
Public
RING COUNTER

4 bit parallel adder/subtractor

4 bit parallel adder/subtractor
Public
4 bit parallel adder/subtractor

Ripple carry subtractor

Ripple carry subtractor
Public
Ripple carry subtractor

FULL SUBSTRACTOR USING NAND GATES

FULL SUBSTRACTOR USING NAND GATES
Public
FULL SUBSTRACTOR USING NAND GATES

BINARY TO GRAY CODE USING BASIC GATES

BINARY TO GRAY CODE USING BASIC GATES
Public
BINARY TO GRAY CODE USING BASIC GATES

BCD TO DECIMAL DECODER

BCD TO DECIMAL DECODER
Public
BCD TO DECIMAL DECODER

16X1 MUX

16X1 MUX
Public
16X1 MUX

32 X 1 MUX USING 4 X 1 MUX

32 X 1 MUX USING 4 X 1 MUX
Public
32 X 1 MUX USING 4 X 1 MUX

nand gate

nand gate
Public
nand gate

CONSENSES THEOREM

CONSENSES THEOREM
Public
CONSENSES THEOREM

DISTRIBUTIVE LAW

DISTRIBUTIVE LAW
Public
DISTRIBUTIVE LAW

1 X 8 DEMUX

1 X 8 DEMUX
Public
1 X 8 DEMUX

1 X 16 DEMUX WRONG ONE

1 X 16 DEMUX WRONG ONE
Public
1 X 16 DEMUX WRONG ONE

4 TO 16 DECODER

4 TO 16 DECODER
Public
4 TO 16 DECODER

FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
Public
FULL ADDER USING BASIC GATES
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