Member since: 4 years
Educational Institution: Not Entered
Country: Not Entered
SYNCHRONOUS UP COUNTER
SYNCHRONOUS UP COUNTERUNIVERSAL SHIFT COUNTER
UNIVERSAL SHIFT COUNTER4.TFF USING SRFF
4.TFF USING SRFF11. JKFF USING DFF
11. JKFF USING DFF9. SRFF USING DFF
9. SRFF USING DFFNAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOPNOR GATE
NOR GATENOT GATE
NOT GATEBoolean Laws Of Addition
Boolean Laws Of AdditionEXOR 2X1 MUX
EXOR 2X1 MUXFULL SUBSTRACTOR USING USING BASIC GATES
FULL SUBSTRACTOR USING USING BASIC GATESAND 2 TO 1 MUX
AND 2 TO 1 MUXBCD ADDER USING IC7483
BCD ADDER USING IC748332 X 1 MUX USING 4 X 1 MUX
32 X 1 MUX USING 4 X 1 MUXSYNCHRONOUS UP/DOWN COUNTER
SYNCHRONOUS UP/DOWN COUNTERAsynchronous 4 bit ripple down counter
Asynchronous 4 bit ripple down counterNOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOPFULL SUBTRACTOR USING XOR GATE
FULL SUBTRACTOR USING XOR GATEUSING 16 X 1 MUX
USING 16 X 1 MUXDONT KNOW
DONT KNOWFULL SUBSTRACTOR USING NOR GATE
FULL SUBSTRACTOR USING NOR GATESYNCHRONOUS UP DOWN CIRCUIT
SYNCHRONOUS UP DOWN CIRCUIT1 X 8 DEMUX
1 X 8 DEMUXHALF ADDER USING XOR GATE
HALF ADDER USING XOR GATEPARALLEL IN PARALLEL OUT SHIFT REGISTER
PARALLEL IN PARALLEL OUT SHIFT REGISTEREXCESS TO BCD CONVERTER
EXCESS TO BCD CONVERTERNAND 2X1 MUX
NAND 2X1 MUXBCD TO EXCESS-3 CONVERTER
BCD TO EXCESS-3 CONVERTER4 TO 1 MUX
4 TO 1 MUXUSING 8 X 1 MUX
USING 8 X 1 MUXSYNCHRONOUS DOWN COUNTER
SYNCHRONOUS DOWN COUNTER1 X 4 MUX
1 X 4 MUX3 TO 8 DECODER
3 TO 8 DECODERINCOMPLETE
INCOMPLETEUntitled
UntitledFULL ADDER USING BASIC GATES
FULL ADDER USING BASIC GATES16X1 MUX
16X1 MUXBCD ADDER
BCD ADDERHALF SUBTRACTOR USING NOR GATE
HALF SUBTRACTOR USING NOR GATEHALF ADDER USING NAND GATES
HALF ADDER USING NAND GATES5. TFF USING JKFF
5. TFF USING JKFFMOD 12 COUNTER
MOD 12 COUNTER7. SRFF USING JKFF
7. SRFF USING JKFF12. JK FF USING TFF
12. JK FF USING TFF24 X 1 MUX USING 8 X 1 MUX
24 X 1 MUX USING 8 X 1 MUXNOR 2X1 MUX
NOR 2X1 MUXXNOR GATE
XNOR GATEFULL SUBSTRACTOR USING NAND GATES
FULL SUBSTRACTOR USING NAND GATEST FLIPFLOP USING LOGIC GATES
T FLIPFLOP USING LOGIC GATES4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUT
4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTCONSENSES THEOREM
CONSENSES THEOREMxor gate
xor gateRING COUNTER
RING COUNTER4 BIT PARITY GENERATOR
4 BIT PARITY GENERATORBCD TO DECIMAL DECODER
BCD TO DECIMAL DECODER4 bit full adder 1
4 bit full adder 1MOD 7 COUNTER
MOD 7 COUNTEROR 2 TO 1 MUX
OR 2 TO 1 MUXMOD 7 COUNTER
MOD 7 COUNTER4 TO 16 DECODER
4 TO 16 DECODERRING COUNTER
RING COUNTER3.DFF USING TFF
3.DFF USING TFFnand gate
nand gate8 X 3 OCTAL TO BINARY ENCODER
8 X 3 OCTAL TO BINARY ENCODERAND GATE
AND GATERipple carry subtractor
Ripple carry subtractor3 BIT PARITY CHECKER
3 BIT PARITY CHECKERHALF ADDER USING NOR GATES
HALF ADDER USING NOR GATESSERIAL IN SERIAL OUT SHIFT REGISTER
SERIAL IN SERIAL OUT SHIFT REGISTERHALF SUBTRACTOR USING XOR GATE
HALF SUBTRACTOR USING XOR GATEFULL ADDER USING NOR GATES
FULL ADDER USING NOR GATESNOT 2X1 MUX
NOT 2X1 MUX2 BIT MADNITUDE COMPARATOR
2 BIT MADNITUDE COMPARATORquestion 6
question 6Untitled
UntitledOR GATE
OR GATE1 X 2 DEMUX
1 X 2 DEMUX10. JKK USING SRFF
10. JKK USING SRFFCOMMUTATIVE LAW
COMMUTATIVE LAW8. SRFF USING TFF
8. SRFF USING TFFBCD ADDER 1
BCD ADDER 13 BIT PARITY GENERATOR
3 BIT PARITY GENERATORSYNCHRONOUS DOWN COUNTER
SYNCHRONOUS DOWN COUNTERSYNCHRONOUS GENERATOR USING COUNTER
SYNCHRONOUS GENERATOR USING COUNTER4 TO 2 ENCODER
4 TO 2 ENCODER2.DIFF USING JKFF
2.DIFF USING JKFFJK FLIPFLOP USING INBUILT
JK FLIPFLOP USING INBUILTMOD 12 COUNTER
MOD 12 COUNTERASYNCHRONOUS 4 BIT RIPPLE COUNTER
ASYNCHRONOUS 4 BIT RIPPLE COUNTER8. SRFF USING TFF
8. SRFF USING TFFSERIAL IN PARALLEL OUT SHIFT REGISTER
SERIAL IN PARALLEL OUT SHIFT REGISTERUntitled
Untitled2X1 MUX
2X1 MUX8 X 3 OCTAL TO BINARY ENCODER
8 X 3 OCTAL TO BINARY ENCODERBINARY TO GRAY CODE USING BASIC GATES
BINARY TO GRAY CODE USING BASIC GATES4 BIT RIPPLE UP/DOWN COUNTER
4 BIT RIPPLE UP/DOWN COUNTERmod 10 counter
mod 10 counterCircuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0
Circuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0USING 4 X 1 MUX
USING 4 X 1 MUXBCD ADDER
BCD ADDERIMPLEMENTATION USING MINTERMS WITH 2:1 MUX
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX4 BIT PARITY CHECKER
4 BIT PARITY CHECKERASSOCIATIVE LAW
ASSOCIATIVE LAWJK FLIPFLOP USING INBUILT
JK FLIPFLOP USING INBUILT6. TFF USING DFF
6. TFF USING DFF4 bit parallel adder/subtractor
4 bit parallel adder/subtractorSHIFT COUNTER
SHIFT COUNTER1 TO 2 DECODER
1 TO 2 DECODER1. DIFF USING SRFF
1. DIFF USING SRFFDISTRIBUTIVE LAW
DISTRIBUTIVE LAWUNIVERSAL SHIFT COUNTER
UNIVERSAL SHIFT COUNTERSR FLIPFLOP USING INBUILT
SR FLIPFLOP USING INBUILTDECIMAL TO BCD ENCODER
DECIMAL TO BCD ENCODERSHIFT COUNTER
SHIFT COUNTERHALF ADDER USING BASIC GATES
HALF ADDER USING BASIC GATESBCD TO EXCESS -3 CONVERTER
BCD TO EXCESS -3 CONVERTERD FLIPFLOP USING LOGIC GATE
D FLIPFLOP USING LOGIC GATE2 X 1 ENCODER
2 X 1 ENCODER2 TO 4 DECODER
2 TO 4 DECODERHALF SUBTRACTOR USING BASIC GATES
HALF SUBTRACTOR USING BASIC GATES4 X 2 PRIORITY ENCODER
4 X 2 PRIORITY ENCODERGRAY TO BINARY CODE CONVERTER
GRAY TO BINARY CODE CONVERTER1 X 16 DEMUX WRONG ONE
1 X 16 DEMUX WRONG ONET FLIPFLOP USING INBUILT
T FLIPFLOP USING INBUILTBOOLEAN LAWS OF MULTIPLICATION
BOOLEAN LAWS OF MULTIPLICATIONDEMORGANS LAW
DEMORGANS LAWBCD TO 7 SEGMENT DECODER
BCD TO 7 SEGMENT DECODERQUESTION 7
QUESTION 7HALF SUBTRACTOR USING NAND GATE
HALF SUBTRACTOR USING NAND GATEABSORPTION LAW
ABSORPTION LAWJACK KILBY FLIPFLOP USING LOGICGATES
JACK KILBY FLIPFLOP USING LOGICGATESFULL ADDER USING XOR GATE
FULL ADDER USING XOR GATEFULL ADDER USING NAND GATE
FULL ADDER USING NAND GATE1 BIT MAGNITUDE COMPARATOR
1 BIT MAGNITUDE COMPARATORDELAY FLIPFLOP USING INBUILT
DELAY FLIPFLOP USING INBUILTFULL ADDER USING BASIC GATES
FULL ADDER USING BASIC GATESmod 12 counter
mod 12 counterasynchronous 4 bit ripple counter with decoded output
asynchronous 4 bit ripple counter with decoded output4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER
4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER