SYNCHRONOUS UP COUNTER

UNIVERSAL SHIFT COUNTER

4.TFF USING SRFF

11. JKFF USING DFF

9. SRFF USING DFF

NAND BASED SR FLIPFLOP

NOR GATE

NOT GATE

Boolean Laws Of Addition

EXOR 2X1 MUX

FULL SUBSTRACTOR USING USING BASIC GATES

AND 2 TO 1 MUX

BCD ADDER USING IC7483

32 X 1 MUX USING 4 X 1 MUX

SYNCHRONOUS UP/DOWN COUNTER

Asynchronous 4 bit ripple down counter

NOR BASED SR FLIPFLOP

FULL SUBTRACTOR USING XOR GATE

USING 16 X 1 MUX

DONT KNOW

FULL SUBSTRACTOR USING NOR GATE

SYNCHRONOUS UP DOWN CIRCUIT

1 X 8 DEMUX

HALF ADDER USING XOR GATE

PARALLEL IN PARALLEL OUT SHIFT REGISTER

EXCESS TO BCD CONVERTER

NAND 2X1 MUX

BCD TO EXCESS-3 CONVERTER

FULL ADDER USING XOR GATE

4 TO 1 MUX

USING 8 X 1 MUX

SYNCHRONOUS DOWN COUNTER

1 X 4 MUX

3 TO 8 DECODER

1 BIT MAGNITUDE COMPARATOR

INCOMPLETE

Untitled

FULL ADDER USING BASIC GATES

16X1 MUX

BCD ADDER

HALF SUBTRACTOR USING NOR GATE

HALF ADDER USING NAND GATES

4 BIT RIPPLE UP/DOWN ASYNCHRONOUS COUNTER

5. TFF USING JKFF

MOD 12 COUNTER

7. SRFF USING JKFF

12. JK FF USING TFF

24 X 1 MUX USING 8 X 1 MUX

NOR 2X1 MUX

XNOR GATE

FULL SUBSTRACTOR USING NAND GATES

T FLIPFLOP USING LOGIC GATES

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUT

CONSENSES THEOREM

SERIAL IN PARALLEL OUT SHIFT REGISTER

xor gate

mod 12 counter

RING COUNTER

4 BIT PARITY GENERATOR

BCD TO DECIMAL DECODER

4 bit full adder 1

FULL ADDER USING BASIC GATES

MOD 7 COUNTER

OR 2 TO 1 MUX

MOD 7 COUNTER

4 TO 16 DECODER

RING COUNTER

3.DFF USING TFF

nand gate

8 X 3 OCTAL TO BINARY ENCODER

AND GATE

Ripple carry subtractor

3 BIT PARITY CHECKER

HALF ADDER USING NOR GATES

SERIAL IN SERIAL OUT SHIFT REGISTER

HALF SUBTRACTOR USING XOR GATE

FULL ADDER USING NOR GATES

NOT 2X1 MUX

2 BIT MADNITUDE COMPARATOR

question 6

Untitled

OR GATE

1 X 2 DEMUX

10. JKK USING SRFF

COMMUTATIVE LAW

8. SRFF USING TFF

BCD ADDER 1

3 BIT PARITY GENERATOR

SYNCHRONOUS DOWN COUNTER

SYNCHRONOUS GENERATOR USING COUNTER

4 TO 2 ENCODER

2.DIFF USING JKFF

JK FLIPFLOP USING INBUILT

MOD 12 COUNTER

ASYNCHRONOUS 4 BIT RIPPLE COUNTER

8. SRFF USING TFF

Untitled

2X1 MUX

DELAY FLIPFLOP USING INBUILT

8 X 3 OCTAL TO BINARY ENCODER

BINARY TO GRAY CODE USING BASIC GATES

4 BIT RIPPLE UP/DOWN COUNTER

mod 10 counter

Circuit that counts (0,2,4...14) When input is 1 and Counts (1,3...15)When input is 0

USING 4 X 1 MUX

BCD ADDER

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX

4 BIT PARITY CHECKER

ASSOCIATIVE LAW

JK FLIPFLOP USING INBUILT

6. TFF USING DFF

asynchronous 4 bit ripple counter with decoded output

4 bit parallel adder/subtractor

SHIFT COUNTER

1 TO 2 DECODER

1. DIFF USING SRFF

DISTRIBUTIVE LAW

UNIVERSAL SHIFT COUNTER

SR FLIPFLOP USING INBUILT

FULL ADDER USING NAND GATE

DECIMAL TO BCD ENCODER

SHIFT COUNTER

HALF ADDER USING BASIC GATES

BCD TO EXCESS -3 CONVERTER

D FLIPFLOP USING LOGIC GATE

2 X 1 ENCODER

2 TO 4 DECODER

HALF SUBTRACTOR USING BASIC GATES

4 X 2 PRIORITY ENCODER

GRAY TO BINARY CODE CONVERTER

1 X 16 DEMUX WRONG ONE

T FLIPFLOP USING INBUILT

BOOLEAN LAWS OF MULTIPLICATION

DEMORGANS LAW

BCD TO 7 SEGMENT DECODER

QUESTION 7

HALF SUBTRACTOR USING NAND GATE

ABSORPTION LAW

JACK KILBY FLIPFLOP USING LOGICGATES