project.name

Raghavi P.S

Member since: 4 years

Educational Institution: Not Entered

Country: India

OR GATE

OR GATE
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2-1 Multiplexer

2-1 Multiplexer
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MUX

MUX
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FLIPFLOPSS

FLIPFLOPSS
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ASSOCIATIVE PROPERTY

ASSOCIATIVE PROPERTY
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Absorption theorum

Absorption theorum
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Associative property

Associative property
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Full Subtractor using NAND gate

Full Subtractor using NAND gate
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Full Subtractor

Full Subtractor
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8 bit parity checker

8 bit parity checker
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8 to 1 MUX

8 to 1 MUX
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1:16 DEMUX

1:16 DEMUX
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MOD 12 COUNTER

MOD 12 COUNTER
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Multiplexers

Multiplexers
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adder 2

adder 2
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adder

adder
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half adder

half adder
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adder

adder
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EX-3

EX-3
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CODE CONVERTORS

CODE CONVERTORS
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ADDER

ADDER
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FULL ADDER

FULL ADDER
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Mux 8to 1

Mux 8to 1
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T FLIP FLOP Using SR FLIP FLOP

T FLIP FLOP Using SR FLIP FLOP
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8 to 3 Priority Encoder

8 to 3 Priority Encoder
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T FLIP FLOP

T FLIP FLOP
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PARALLEL IN PARALLEL OUT

PARALLEL IN PARALLEL OUT
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Distributive law

Distributive law
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D flipflop using nand gate

D flipflop using nand gate
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D FLIP FLOP USING SR FLIP FLOP

D FLIP FLOP USING SR FLIP FLOP
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serial in serial out

serial in serial out
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CODE CONVERTER

CODE CONVERTER
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4 : 1 multiplexer

4 : 1 multiplexer
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Mux 4:1

Mux 4:1
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jk flip flop using nand gate

jk flip flop using nand gate
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clocked rs flip flop using nand gate

clocked rs flip flop using nand gate
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rs flip flop using nand gate

rs flip flop using nand gate
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rs flip flop using nand gate

rs flip flop using nand gate
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REMAINING

REMAINING
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T FLIP FLOP USING D FLIP FLOP

T FLIP FLOP USING D FLIP FLOP
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JK FLIP FLOP USING T FLIP FLOP

JK FLIP FLOP USING T FLIP FLOP
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D FLIP FLOP using JK FLIP FLOP

D FLIP FLOP using JK FLIP FLOP
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4 bit ripple down counter

4 bit ripple down counter
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MOD 12 COUNTER

MOD 12 COUNTER
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Consensus Theorem

Consensus Theorem
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SHIFT COUNTER

SHIFT COUNTER
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Consensus Theorem

Consensus Theorem
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Distributive law

Distributive law
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CONSENSUS THEOREM

CONSENSUS THEOREM
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FULL ADDER

FULL ADDER
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Full substractor

Full substractor
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full adder using nand gate

full adder using nand gate
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Half Adder using NOR Gates

Half Adder using NOR Gates
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half adder using nand gates

half adder using nand gates
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Gray code to Binary code conversion

Gray code to Binary code conversion
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BCD to Excess-3 Code Converter

BCD to Excess-3 Code Converter
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8-bit comparator

8-bit comparator
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1 to 2 Demultiplexer

1 to 2 Demultiplexer
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2 to 1 MUX

2 to 1 MUX
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16 to 1 Multiplexer

16 to 1 Multiplexer
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4 to 1 MUX

4 to 1 MUX
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BCD to Decimal Decoder

BCD to Decimal Decoder
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PARALLEL IN SERIAL OUT

PARALLEL IN SERIAL OUT
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SHIFT COUNTER

SHIFT COUNTER
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REMAINING

REMAINING
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SERIAL IN SERIAL OUT

SERIAL IN SERIAL OUT
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synchronous up/down counter

synchronous up/down counter
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SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
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RING COUNTER

RING COUNTER
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shift counter

shift counter
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Full Adder using NOR Gate

Full Adder using NOR Gate
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COMMUTATIVE PROPERTY

COMMUTATIVE PROPERTY
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HALF SUBTRACTOR USING NOR GATE

HALF SUBTRACTOR USING NOR GATE
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CODE CONVERTORS

CODE CONVERTORS
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gate

gate
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Untitled

Untitled
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AND GATE

AND GATE
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OR GATE

OR GATE
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OR GATE

OR GATE
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NOR GATE

NOR GATE
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EX-OR GATE

EX-OR GATE
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EXNOR-GATE

EXNOR-GATE
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DECODERS

DECODERS
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BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
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parity

parity
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one

one
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4-BIT PARITY GENERATOR

4-BIT PARITY GENERATOR
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FA-BASIC

FA-BASIC
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half adder

half adder
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3 TO 8 DECODER

3 TO 8 DECODER
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FULL SUB

FULL SUB
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DeMorgan's theorem

DeMorgan's theorem
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4-bit Magnitude comparator

4-bit Magnitude comparator
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NAND GATE

NAND GATE
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NAND GATE

NAND GATE
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SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
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T FLIP FLOP Using JK FLIP FLOP

T FLIP FLOP Using JK FLIP FLOP
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4 bit ripple down counter

4 bit ripple down counter
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FULL ADDER

FULL ADDER
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Associative property

Associative property
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BCD ADDER

BCD ADDER
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JK FLIP FLOP USING SR FLIP FLOP

JK FLIP FLOP USING SR FLIP FLOP
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D FLIP FLOP Using T FLIP FLOP

D FLIP FLOP Using T FLIP FLOP
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SR FLIP FLOP USING T FLIP FLOP

SR FLIP FLOP USING T FLIP FLOP
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SR FLIP FLOP USING JK FLIP FLOP

SR FLIP FLOP USING JK FLIP FLOP
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4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS

4 BIT RIPPLE UP COUNTER WITH DECODED OUTPUTS
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Universal Shift Register

Universal Shift Register
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HALF SUBTRACTOR USING NAND GATE

HALF SUBTRACTOR USING NAND GATE
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parity generators

parity generators
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4-bit Magnitude comparator

4-bit Magnitude comparator
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SR FLIP FLOP USING T FLIP FLOP

SR FLIP FLOP USING T FLIP FLOP
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full adder using nand gate

full adder using nand gate
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Full Subtractor using NAND gate

Full Subtractor using NAND gate
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4 Bit magnitude comparator

4 Bit magnitude comparator
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