project.name

Ashok Sandeep N.B.S

Member since: 3 years

Educational Institution: Mepco Schlenk Engineering College

Country: India

PISO

PISO
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NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
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FULL SUBTRACTOR

FULL SUBTRACTOR
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4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
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4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
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DFF USING TFF

DFF USING TFF
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DFF USING JKFF

DFF USING JKFF
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JKFF USING DFF

JKFF USING DFF
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TFF USING SRFF

TFF USING SRFF
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Ripple carry Adder

Ripple carry Adder
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BCD ADDER

BCD ADDER
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Binary to gray code converter

Binary to gray code converter
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D FLIPFLOP

D FLIPFLOP
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3 BIT PARITY CHECKER

3 BIT PARITY CHECKER
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D FLIPFLOP

D FLIPFLOP
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T FLIPFLOP

T FLIPFLOP
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SRFF using DFF

SRFF using DFF
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MOD 7 COUNTER

MOD 7 COUNTER
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16 to 1 MUX

16 to 1 MUX
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ABSORPTION LAW 3

ABSORPTION LAW 3
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ABSORPTION LAW 3

ABSORPTION LAW 3
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3 BIT PARITY GENERATOR

3 BIT PARITY GENERATOR
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4 BIT PARITY GENERATOR

4 BIT PARITY GENERATOR
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4 bit synchronous counter

4 bit synchronous counter
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24 TO 1 MUX USING 1 MUX

24 TO 1 MUX USING 1 MUX
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16 to 1 MUX

16 to 1 MUX
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16 to 1 MUX

16 to 1 MUX
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
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NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
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CONSENSUS LAW 2

CONSENSUS LAW 2
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DISTRIBUTIVE PROPERTY

DISTRIBUTIVE PROPERTY
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DE MORGANS THEORM 2

DE MORGANS THEORM 2
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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ASSOCIATIVE LAW OF ADDITION

ASSOCIATIVE LAW OF ADDITION
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Demorgans theorem-I

Demorgans theorem-I
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COMMUTATIVE LAW OF MULTIPLICATION

COMMUTATIVE LAW OF MULTIPLICATION
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DE MORGANS THEORM 1

DE MORGANS THEORM 1
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counter having the states 0-2--4-7-0

counter having the states 0-2--4-7-0
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4 bit bidirectional shift register

4 bit bidirectional shift register
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project.name
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SIPO

SIPO
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16 to 1 MUX

16 to 1 MUX
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IMPLEMENTATION USING MUX(1)

IMPLEMENTATION USING MUX(1)
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ASSOCIATIVE LAW OF MULTIPLICATION

ASSOCIATIVE LAW OF MULTIPLICATION
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ABSORPTION LAW 4

ABSORPTION LAW 4
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NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
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project.name
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TFF USING JKFF

TFF USING JKFF
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Boolean postulates and law

Boolean postulates and law
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Demorgans theprem-II

Demorgans theprem-II
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1-bit magnitude comparitor

1-bit magnitude comparitor
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4 to 2 priority encoder

4 to 2 priority encoder
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VERFICATION OF BOOLEAN LAWS AND POSTULATES

VERFICATION OF BOOLEAN LAWS AND POSTULATES
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project.name
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2 x 4 DECODER

2 x 4 DECODER
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Gray to binary code converter

Gray to binary code converter
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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3 bit binary counter

3 bit binary counter
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sequence generator using counter

sequence generator using counter
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mod-6 unit distance counter

mod-6 unit distance counter
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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
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SISO

SISO
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JKFlip

JKFlip
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de morgans theorem

de morgans theorem
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AS adder/subtractor

AS adder/subtractor
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Full Subtractor

Full Subtractor
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Decimal to BCD Encoder

Decimal to BCD Encoder
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4 x 2 ENCODER

4 x 2 ENCODER
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1 to 16 DEMUX

1 to 16 DEMUX
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4 to 2 priority encoder

4 to 2 priority encoder
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1 x 2 DECODER

1 x 2 DECODER
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3 x 8 DECODER

3 x 8 DECODER
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16 to 1 MUX

16 to 1 MUX
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8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
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2 to 4 Decoder

2 to 4 Decoder
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8 to 1 mux

8 to 1 mux
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2 x 1 ENCODER

2 x 1 ENCODER
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IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
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project.name
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4 bit synchronous counter with ripple carry

4 bit synchronous counter with ripple carry
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Half adder

Half adder
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16 bit parity generator

16 bit parity generator
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16-Bit Parity checker

16-Bit Parity checker
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AS adder/subtractor

AS adder/subtractor
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2 bit MC

2 bit MC
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1 bit MC

1 bit MC
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Half subtractor

Half subtractor
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project.name
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JKFF USING DFF

JKFF USING DFF
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project.name
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JKFF Using TFF

JKFF Using TFF
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DFF USING JKFF

DFF USING JKFF
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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project.name
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SRFF USING JKFF

SRFF USING JKFF
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SR FLIPFLOP

SR FLIPFLOP
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TFF

TFF
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JKFF Using TFF

JKFF Using TFF
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homework 1

homework 1
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TFF USING DFF

TFF USING DFF
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project.name
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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INVERSION LAW

INVERSION LAW
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Boolean postulates and law

Boolean postulates and law
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4 bit ripple counter

4 bit ripple counter
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project.name
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Half adder

Half adder
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Full adder

Full adder
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project.name
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BCD to 7 segment decoder

BCD to 7 segment decoder
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project.name
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Octal to Binary Encoder

Octal to Binary Encoder
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project.name
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BCD to Decimal Decoder

BCD to Decimal Decoder
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project.name
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4 to 1 multiplexer

4 to 1 multiplexer
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project.name
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2 to 1 multiplexer

2 to 1 multiplexer
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project.name
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IMPLEMENTATION USING MUX(1)

IMPLEMENTATION USING MUX(1)
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project.name
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2 BIT MAGNITUDE COMPARITOR

2 BIT MAGNITUDE COMPARITOR
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project.name
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16 to 1 MUX

16 to 1 MUX
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4 bit ripple down counter

4 bit ripple down counter
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PIPO

PIPO
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SRFF USING TFF

SRFF USING TFF
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ABSORPTION LAW 1

ABSORPTION LAW 1
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project.name
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4 bit synchronous up counter

4 bit synchronous up counter
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CONSENSUS theorem

CONSENSUS theorem
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Half adder

Half adder
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AS adder/subtractor

AS adder/subtractor
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MOD 12 COUNTER

MOD 12 COUNTER
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DFF USING SRFF

DFF USING SRFF
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MUX with counter

MUX with counter
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4 bit synchronous down counter

4 bit synchronous down counter
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MUX with counter

MUX with counter
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name
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JK FLIPFLOP

JK FLIPFLOP
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D FLIPFLOP

D FLIPFLOP
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OR USING 2 TO 1 MUX

OR USING 2 TO 1 MUX
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CONSENSUS THEROEM

CONSENSUS THEROEM
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project.name
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COMMUTATIVE LAW OF ADDITION

COMMUTATIVE LAW OF ADDITION
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project.name
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
Public
project.name
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DISTRIBUTIVE PROPERTY 2

DISTRIBUTIVE PROPERTY 2
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project.name
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4 BIT RIPPLE UP-DOWN COUNTER

4 BIT RIPPLE UP-DOWN COUNTER
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project.name
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4 bit synchronous down counter

4 bit synchronous down counter
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project.name
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Excess -3 to BCD Converter

Excess -3 to BCD Converter
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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16 to 1 MUX

16 to 1 MUX
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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project.name
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BCD to excess-3 converter

BCD to excess-3 converter
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project.name
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ABSORPTION LAW 2

ABSORPTION LAW 2
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implementation of full adder using counter

implementation of full adder using counter
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project.name
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4 bit synchronous counter with ripple carry

4 bit synchronous counter with ripple carry
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JKFF using SRFF

JKFF using SRFF
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