Ashok Sandeep N.B.S
Member since: 4 years
Educational Institution: Mepco Schlenk Engineering College
Country: India
PISO
PISO
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
FULL SUBTRACTOR
FULL SUBTRACTOR
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
DFF USING TFF
DFF USING TFF
DFF USING JKFF
DFF USING JKFF
JKFF USING DFF
JKFF USING DFF
TFF USING SRFF
TFF USING SRFF
Ripple carry Adder
Ripple carry Adder
BCD ADDER
BCD ADDER
Binary to gray code converter
Binary to gray code converter
D FLIPFLOP
D FLIPFLOP
3 BIT PARITY CHECKER
3 BIT PARITY CHECKER
D FLIPFLOP
D FLIPFLOP
T FLIPFLOP
T FLIPFLOP
SRFF using DFF
SRFF using DFF
MOD 7 COUNTER
MOD 7 COUNTER
16 to 1 MUX
16 to 1 MUX
ABSORPTION LAW 3
ABSORPTION LAW 3
ABSORPTION LAW 3
ABSORPTION LAW 3
3 BIT PARITY GENERATOR
3 BIT PARITY GENERATOR
4 BIT PARITY GENERATOR
4 BIT PARITY GENERATOR
4 bit synchronous counter
4 bit synchronous counter
24 TO 1 MUX USING 1 MUX
24 TO 1 MUX USING 1 MUX
16 to 1 MUX
16 to 1 MUX
16 to 1 MUX
16 to 1 MUX
NOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUX
32 TO 1 MUX USING 4 TO 1 MUX
NOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
CONSENSUS LAW 2
CONSENSUS LAW 2
DISTRIBUTIVE PROPERTY
DISTRIBUTIVE PROPERTY
DE MORGANS THEORM 2
DE MORGANS THEORM 2
Verification of Boolean postulates and laws
Verification of Boolean postulates and laws
ASSOCIATIVE LAW OF ADDITION
ASSOCIATIVE LAW OF ADDITION
Demorgans theorem-I
Demorgans theorem-I
COMMUTATIVE LAW OF MULTIPLICATION
COMMUTATIVE LAW OF MULTIPLICATION
DE MORGANS THEORM 1
DE MORGANS THEORM 1
counter having the states 0-2--4-7-0
counter having the states 0-2--4-7-0
4 bit bidirectional shift register
4 bit bidirectional shift register
SIPO
SIPO
16 to 1 MUX
16 to 1 MUX
IMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)
ASSOCIATIVE LAW OF MULTIPLICATION
ASSOCIATIVE LAW OF MULTIPLICATION
ABSORPTION LAW 4
ABSORPTION LAW 4
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
TFF USING JKFF
TFF USING JKFF
Boolean postulates and law
Boolean postulates and law
Demorgans theprem-II
Demorgans theprem-II
1-bit magnitude comparitor
1-bit magnitude comparitor
4 to 2 priority encoder
4 to 2 priority encoder
VERFICATION OF BOOLEAN LAWS AND POSTULATES
VERFICATION OF BOOLEAN LAWS AND POSTULATES
2 x 4 DECODER
2 x 4 DECODER
Gray to binary code converter
Gray to binary code converter
4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTER
3 bit binary counter
3 bit binary counter
sequence generator using counter
sequence generator using counter
mod-6 unit distance counter
mod-6 unit distance counter
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
SISO
SISO
JKFlip
JKFlip
de morgans theorem
de morgans theorem
AS adder/subtractor
AS adder/subtractor
Full Subtractor
Full Subtractor
Decimal to BCD Encoder
Decimal to BCD Encoder
4 x 2 ENCODER
4 x 2 ENCODER
1 to 16 DEMUX
1 to 16 DEMUX
4 to 2 priority encoder
4 to 2 priority encoder
1 x 2 DECODER
1 x 2 DECODER
3 x 8 DECODER
3 x 8 DECODER
16 to 1 MUX
16 to 1 MUX
8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
2 to 4 Decoder
2 to 4 Decoder
8 to 1 mux
8 to 1 mux
2 x 1 ENCODER
2 x 1 ENCODER
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
Half adder
Half adder
16 bit parity generator
16 bit parity generator
16-Bit Parity checker
16-Bit Parity checker
AS adder/subtractor
AS adder/subtractor
2 bit MC
2 bit MC
1 bit MC
1 bit MC
Half subtractor
Half subtractor
JKFF USING DFF
JKFF USING DFF
JKFF Using TFF
JKFF Using TFF
DFF USING JKFF
DFF USING JKFF
implementation of full adder with mux and counter
implementation of full adder with mux and counter
SRFF USING JKFF
SRFF USING JKFF
SR FLIPFLOP
SR FLIPFLOP
TFF
TFF
JKFF Using TFF
JKFF Using TFF
homework 1
homework 1
TFF USING DFF
TFF USING DFF
4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN counter
INVERSION LAW
INVERSION LAW
Boolean postulates and law
Boolean postulates and law
4 bit ripple counter
4 bit ripple counter
Half adder
Half adder
Full adder
Full adder
BCD to 7 segment decoder
BCD to 7 segment decoder
Octal to Binary Encoder
Octal to Binary Encoder
BCD to Decimal Decoder
BCD to Decimal Decoder
4 to 1 multiplexer
4 to 1 multiplexer
2 to 1 multiplexer
2 to 1 multiplexer
2 BIT MAGNITUDE COMPARITOR
2 BIT MAGNITUDE COMPARITOR
16 to 1 MUX
16 to 1 MUX
4 bit ripple down counter
4 bit ripple down counter
PIPO
PIPO
SRFF USING TFF
SRFF USING TFF
ABSORPTION LAW 1
ABSORPTION LAW 1
4 bit synchronous up counter
4 bit synchronous up counter
CONSENSUS theorem
CONSENSUS theorem
Half adder
Half adder
AS adder/subtractor
AS adder/subtractor
MOD 12 COUNTER
MOD 12 COUNTER
DFF USING SRFF
DFF USING SRFF
MUX with counter
MUX with counter
4 bit synchronous down counter
4 bit synchronous down counter
MUX with counter
MUX with counter
implementation of full adder with mux and counter
implementation of full adder with mux and counter
JK FLIPFLOP
JK FLIPFLOP
D FLIPFLOP
D FLIPFLOP
OR USING 2 TO 1 MUX
OR USING 2 TO 1 MUX
CONSENSUS THEROEM
CONSENSUS THEROEM
COMMUTATIVE LAW OF ADDITION
COMMUTATIVE LAW OF ADDITION
Verification of Boolean postulates and laws
Verification of Boolean postulates and laws
DISTRIBUTIVE PROPERTY 2
DISTRIBUTIVE PROPERTY 2
4 BIT RIPPLE UP-DOWN COUNTER
4 BIT RIPPLE UP-DOWN COUNTER
4 bit synchronous down counter
4 bit synchronous down counter
Excess -3 to BCD Converter
Excess -3 to BCD Converter
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
16 to 1 MUX
16 to 1 MUX
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
BCD to excess-3 converter
BCD to excess-3 converter
ABSORPTION LAW 2
ABSORPTION LAW 2
implementation of full adder using counter
implementation of full adder using counter
4 bit synchronous counter with ripple carry
4 bit synchronous counter with ripple carry
JKFF using SRFF
JKFF using SRFF
IMPLEMENTATION USING MUX(1)
IMPLEMENTATION USING MUX(1)
4 bit synchronous counter with ripple carry
4 bit synchronous counter with ripple carry
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