Pooja K
Member since: 4 years
Educational Institution: Not Entered
Country: Not Entered
X+YZ=(X+Y)(X+Z)
X+YZ=(X+Y)(X+Z)
PARITY GENERATOR AND CHECKER
PARITY GENERATOR AND CHECKER
DECIMAL TO BCD PRIORITY ENCODER
DECIMAL TO BCD PRIORITY ENCODER
3 BIT PARITY CHECKER VIII
3 BIT PARITY CHECKER VIII
4 bit parity generator VIII
4 bit parity generator VIII
8 TO 1 MUX IV
8 TO 1 MUX IV
JK Flipflop
JK Flipflop
DFF using SRFF
DFF using SRFF
DFF using TFF
DFF using TFF
NOR based SR flipflop
NOR based SR flipflop
NAND based SR flipflop
NAND based SR flipflop
Untitled
Untitled
T FF
T FF
D flipflop
D flipflop
TFF using SRFF
TFF using SRFF
TFF using DFF
TFF using DFF
SRFF using TFF
SRFF using TFF
JKFF using SRFF
JKFF using SRFF
JKFF using DFF
JKFF using DFF
Untitled
Untitled
16 to 1 Mux
16 to 1 Mux
16 to 1 Mux
16 to 1 Mux
8 BIT ODD/ EVEN PARITY
8 BIT ODD/ EVEN PARITY
BCD to excess- 3 converter
BCD to excess- 3 converter
1 TO 2 DECODER
1 TO 2 DECODER
1 TO 4 DEMUX
1 TO 4 DEMUX
1 TO 8 DEMUX
1 TO 8 DEMUX
4 TO 1 MULTIPLEXER
4 TO 1 MULTIPLEXER
Full adder using basic gates
Full adder using basic gates
24 TO 1 MUX USING 8 TO 1 MUX
24 TO 1 MUX USING 8 TO 1 MUX
8 TO 1 MUX IV
8 TO 1 MUX IV
MOD 6 UNIT DISTANCE COUNTER
MOD 6 UNIT DISTANCE COUNTER
Full Adder
Full Adder
Untitled
Untitled
3 TO 8 DECODER
3 TO 8 DECODER
4 BIT RIPPLE COUNTER
4 BIT RIPPLE COUNTER
MOD 12 COUNTER
MOD 12 COUNTER
16 to 1 Mux
16 to 1 Mux
serial in serial out
serial in serial out
SEQUENCE GENERATOR USING COUNTER
SEQUENCE GENERATOR USING COUNTER
3 BIT BINARY COUNTER
3 BIT BINARY COUNTER
COUNTER THAT COUNTS 0,2,4,7,0
COUNTER THAT COUNTS 0,2,4,7,0
Demorgans law
Demorgans law
Boolean laws of multiplication
Boolean laws of multiplication
Untitled
Untitled
1 to 2 Demux
1 to 2 Demux
3 BIT PARITY GENERATOR II
3 BIT PARITY GENERATOR II
ExOR
ExOR
OR Gate
OR Gate
AND Gate
AND Gate
NOR
NOR
Decimal to BCD Encoder
Decimal to BCD Encoder
Distributive law
Distributive law
Commutative law
Commutative law
commutative law
commutative law
4 TO 2 PRIORITY ENCODER
4 TO 2 PRIORITY ENCODER
Ripple Carry Subtractor
Ripple Carry Subtractor
2 TO 1 ENCODER
2 TO 1 ENCODER
Full adder
Full adder
FA
FA
Untitled
Untitled
3 TO 8 DECODER
3 TO 8 DECODER
4 to 16 Decoder
4 to 16 Decoder
FS
FS
Gray to Binary Code VIII
Gray to Binary Code VIII
Consenses theorem
Consenses theorem
BCD to 7 Segment Decoder
BCD to 7 Segment Decoder
16 to 1 MUX II
16 to 1 MUX II
Untitled
Untitled
JKFF using TFF
JKFF using TFF
SRFF using DFF
SRFF using DFF
Binary to Gray code VIII
Binary to Gray code VIII
OCTAL TO BINARY ENCODER
OCTAL TO BINARY ENCODER
4 TO 2 ENCODER
4 TO 2 ENCODER
Boolean laws of addition
Boolean laws of addition
16 to 1 Mux
16 to 1 Mux
1 BIT MAGNITUDE COMPARATOR II
1 BIT MAGNITUDE COMPARATOR II
Full adder using NAND gate
Full adder using NAND gate
BCD TO EXCESS 3 CODE
BCD TO EXCESS 3 CODE
Verification of truth table using AND gate
Verification of truth table using AND gate
16 to 1 Mux
16 to 1 Mux
2 TO 1 MULTIPLEXER
2 TO 1 MULTIPLEXER
NOT
NOT
NAND
NAND
ExNOR
ExNOR
JK flipflop
JK flipflop
PARALLEL IN SERIAL OUT
PARALLEL IN SERIAL OUT
associative law
associative law
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
BCD TO DECIMAL DECODER
BCD TO DECIMAL DECODER
Ripple Carry Adder
Ripple Carry Adder
1 TO 16 DEMUX
1 TO 16 DEMUX
Synchronous counter UP
Synchronous counter UP
16 to 1 Mux
16 to 1 Mux
2 TO 1 MUX
2 TO 1 MUX
SR flipflop
SR flipflop
Verification of truth table using AND gate
Verification of truth table using AND gate
2 TO 4 DECODER
2 TO 4 DECODER
2 BIT MAGNITUDE COMPARATOR XV
2 BIT MAGNITUDE COMPARATOR XV
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