project.name

Helan Raffeal.R

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

FULL ADDER-NAND NAND IMPLEMENTATION

FULL ADDER-NAND NAND IMPLEMENTATION
Public
project.name

8 to 1 MUX

8 to 1 MUX
Public
project.name

BCD ADDER

BCD ADDER
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
Public
project.name

JKFF Using TFF

JKFF Using TFF
Public
project.name

4 bit synchronous down counter

4 bit synchronous down counter
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

SRFF using DFF

SRFF using DFF
Public
project.name

TFF

TFF
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

SRFF USING JKFF

SRFF USING JKFF
Public
project.name

DFF USING TFF

DFF USING TFF
Public
project.name

TFF USING SRFF

TFF USING SRFF
Public
project.name

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION
Public
project.name

2 to 4 Decoder

2 to 4 Decoder
Public
project.name

IMPLEMENTATION USING MUX(1)

IMPLEMENTATION USING MUX(1)
Public
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Demorgans theprem-II

Demorgans theprem-II
Public
project.name

Demorgans theorem

Demorgans theorem
Public
project.name

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
Public
project.name

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
Public
project.name

EX-NOR

EX-NOR
Public
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NAND

NAND
Public
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NOR-gate

NOR-gate
Public
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2 x 1 ENCODER

2 x 1 ENCODER
Public
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4 bit ripple down counter

4 bit ripple down counter
Public
project.name

COMMUTATIVE LAW OF MULTIPLICATION

COMMUTATIVE LAW OF MULTIPLICATION
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
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TFF USING DFF

TFF USING DFF
Public
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1 to 2 DEMUX

1 to 2 DEMUX
Public
project.name

SRFF USING TFF

SRFF USING TFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

SRFF using DFF

SRFF using DFF
Public
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SIPO

SIPO
Public
project.name

4 bit parity generator

4 bit parity generator
Public
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4 bit ripple counter

4 bit ripple counter
Public
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3 bit binary counter

3 bit binary counter
Public
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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
Public
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HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION
Public
project.name

T FLIPFLOP

T FLIPFLOP
Public
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OR USING 2 TO 1 MUX

OR USING 2 TO 1 MUX
Public
project.name

DISTRIBUTIVE PROPERTY

DISTRIBUTIVE PROPERTY
Public
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JKFF using SRFF

JKFF using SRFF
Public
project.name

SR FLIPFLOP

SR FLIPFLOP
Public
project.name

ASSOCIATIVE LAW OF MULTIPLICATION

ASSOCIATIVE LAW OF MULTIPLICATION
Public
project.name

4 x 2 ENCODER

4 x 2 ENCODER
Public
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24 to 1 MUX using 8 to 1 MUX

24 to 1 MUX using 8 to 1 MUX
Public
project.name

Octal to Binary Encoder

Octal to Binary Encoder
Public
project.name

ABSORPTION LAW 1

ABSORPTION LAW 1
Public
project.name

ABSORPTION LAW 3

ABSORPTION LAW 3
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
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4 to 1 MUX

4 to 1 MUX
Public
project.name

4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
Public
project.name

4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

sequence generator using counter

sequence generator using counter
Public
project.name

1 bit Magnitude Comparator

1 bit Magnitude Comparator
Public
project.name

IMPLEMENTATION USING MUX(1)

IMPLEMENTATION USING MUX(1)
Public
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BCD ADDER

BCD ADDER
Public
project.name

16 to 1 mux

16 to 1 mux
Public
project.name

16 to 1 mux

16 to 1 mux
Public
project.name

Untitled

Untitled
Public
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NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
Public
project.name

3 bit parity generator

3 bit parity generator
Public
project.name

Full subtractor using basic gates

Full subtractor using basic gates
Public
project.name

1 x 2 DECODER

1 x 2 DECODER
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

PISO

PISO
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
Public
project.name

4 bit synchronous counter with ripple carry

4 bit synchronous counter with ripple carry
Public
project.name

BCD to 7 segment decoder

BCD to 7 segment decoder
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
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SISO

SISO
Public
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4 bit synchronous counter

4 bit synchronous counter
Public
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
Public
project.name

ABSORPTION LAW 4

ABSORPTION LAW 4
Public
project.name

NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
Public
project.name

ABSORPTION LAW 2

ABSORPTION LAW 2
Public
project.name

ASSOCIATIVE LAW OF ADDITION

ASSOCIATIVE LAW OF ADDITION
Public
project.name

3 x 8 DECODER

3 x 8 DECODER
Public
project.name

2 x 4 DECODER

2 x 4 DECODER
Public
project.name

NOT gate

NOT gate
Public
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32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
Public
project.name

1 x 2 DECODER

1 x 2 DECODER
Public
project.name

EXCESS-3 TO BCD

EXCESS-3 TO BCD
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

AND USING 2 TO 1 MUX

AND USING 2 TO 1 MUX
Public
project.name

DFF USING JKFF

DFF USING JKFF
Public
project.name

HALF SUBTRACTOR-NAND NAND IMPLEMENTATION

HALF SUBTRACTOR-NAND NAND IMPLEMENTATION
Public
project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
Public
project.name

1 to 8 DEMUX

1 to 8 DEMUX
Public
project.name

3 bit Parity Checker

3 bit Parity Checker
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION
Public
project.name

BCD TO EXCESS-3

BCD TO EXCESS-3
Public
project.name

8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
Public
project.name

FULL SUBRACTOR USING NOR GATES

FULL SUBRACTOR USING NOR GATES
Public
project.name

COMMUTATIVE LAW OF ADDITION

COMMUTATIVE LAW OF ADDITION
Public
project.name

OR gate

OR gate
Public
project.name

CONSENSUS THEROEM

CONSENSUS THEROEM
Public
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FULL SUBTRACTOR

FULL SUBTRACTOR
Public
project.name

EX-OR gate

EX-OR gate
Public
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HALF SUBTRACTOR

HALF SUBTRACTOR
Public
project.name

MOD 12 COUNTER

MOD 12 COUNTER
Public
project.name

FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
Public
project.name

ABSORPTION LAW 3

ABSORPTION LAW 3
Public
project.name

NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
Public
project.name

DFF USING SRFF

DFF USING SRFF
Public
project.name

ASSOCIATIVE LAW OF MULTIPLICATION

ASSOCIATIVE LAW OF MULTIPLICATION
Public
project.name

NAND gate

NAND gate
Public
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Decimal to BCD Encoder

Decimal to BCD Encoder
Public
project.name

VERFICATION OF BOOLEAN LAWS AND POSTULATES

VERFICATION OF BOOLEAN LAWS AND POSTULATES
Public
project.name

implementation of full adder using counter

implementation of full adder using counter
Public
project.name

mod-6 unit distance counter

mod-6 unit distance counter
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

TFF USING JKFF

TFF USING JKFF
Public
project.name

4 bit parity checker

4 bit parity checker
Public
project.name

2 bit Magnitude Comparator

2 bit Magnitude Comparator
Public
project.name

PIPO

PIPO
Public
project.name

1 to 4 DEMUX

1 to 4 DEMUX
Public
project.name

Half subtractor using basic gates

Half subtractor using basic gates
Public
project.name

EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
Public
project.name

BCD to Decimal Decoder

BCD to Decimal Decoder
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

AND gate

AND gate
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

4 to 2 priority encoder

4 to 2 priority encoder
Public
project.name

implementation of full adder using counter

implementation of full adder using counter
Public
project.name

MOD 7 COUNTER

MOD 7 COUNTER
Public
project.name
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