FULL ADDER-NAND NAND IMPLEMENTATION

8 to 1 MUX

BCD ADDER

Ripple carry Adder

NAND USING 2 TO 1 MUX

JKFF Using TFF

4 bit synchronous down counter

JK FLIPFLOP

SRFF using DFF

TFF

JK FLIPFLOP

SRFF USING JKFF

DFF USING TFF

TFF USING SRFF

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

2 to 4 Decoder

IMPLEMENTATION USING MUX(1)

Demorgans theprem-II

Demorgans theorem

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER

EX-NOR

NAND

NOR-gate

2 x 1 ENCODER

4 bit ripple down counter

COMMUTATIVE LAW OF MULTIPLICATION

D FLIPFLOP

TFF USING DFF

1 to 2 DEMUX

SRFF USING TFF

JKFF USING DFF

SRFF using DFF

SIPO

4 bit parity generator

4 bit ripple counter

3 bit binary counter

counter that counts 0,2,4,7,0

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

T FLIPFLOP

OR USING 2 TO 1 MUX

DISTRIBUTIVE PROPERTY

JKFF using SRFF

SR FLIPFLOP

ASSOCIATIVE LAW OF MULTIPLICATION

4 x 2 ENCODER

24 to 1 MUX using 8 to 1 MUX

Octal to Binary Encoder

ABSORPTION LAW 1

ABSORPTION LAW 3

2 to 1 MUX

4 to 1 MUX

4 BIT ADDER /SUBTRACTOR

4 BIT UP-DOWN COUNTER

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

sequence generator using counter

1 bit Magnitude Comparator

IMPLEMENTATION USING MUX(1)

BCD ADDER

16 to 1 mux

16 to 1 mux

Untitled

NAND BASED SR FLIPFLOP

3 bit parity generator

Full subtractor using basic gates

1 x 2 DECODER

4 bit ripple counter with decoded outputs

PISO

4 bit ripple counter with decoded outputs

1 to 16 DEMUX

8 TO 3 PRIORITY ENCODER

4 bit synchronous counter with ripple carry

BCD to 7 segment decoder

IMPLEMENTION USING MUX(2)

SISO

4 bit synchronous counter

4 bit synchronous UP/DOWN counter

4 BIT UP-DOWN COUNTER

ABSORPTION LAW 4

NOR USING 2 TO 1 MUX

ABSORPTION LAW 2

3 x 8 DECODER

2 x 4 DECODER

NOT gate

32 to 1 MUX using 4 to 1 MUX

1 x 2 DECODER

EXCESS-3 TO BCD

implementation of full adder with mux and counter

AND USING 2 TO 1 MUX

DFF USING JKFF

HALF SUBTRACTOR-NAND NAND IMPLEMENTATION

4 BIT UNIVERSAL SHIFT REGISTER

1 to 8 DEMUX

3 bit Parity Checker

4 bit synchronous UP/DOWN counter

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

BCD TO EXCESS-3

8 TO 3 PRIORITY ENCODER

FULL SUBRACTOR USING NOR GATES

COMMUTATIVE LAW OF ADDITION

OR gate

CONSENSUS THEROEM

FULL SUBTRACTOR

EX-OR gate

HALF SUBTRACTOR

MOD 12 COUNTER

FULL ADDER USING BASIC GATES

ABSORPTION LAW 3

NOT USING 2 TO 1 MUX

DFF USING SRFF

ASSOCIATIVE LAW OF MULTIPLICATION

NAND gate

Decimal to BCD Encoder

VERFICATION OF BOOLEAN LAWS AND POSTULATES

implementation of full adder using counter

mod-6 unit distance counter

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

RIPPLE CARRY SUBTRACTOR

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

4 bit bidirectional shift register

NOR BASED SR FLIPFLOP

TFF USING JKFF

4 bit parity checker

2 bit Magnitude Comparator

PIPO

1 to 4 DEMUX

Half subtractor using basic gates

EXOR USING 2 TO 1 MUX

BCD to Decimal Decoder

4 bit synchronous UP/DOWN counter

AND gate

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

4 to 2 priority encoder

implementation of full adder using counter

MOD 7 COUNTER

ASSOCIATIVE LAW OF ADDITION