1 bit Magnitude Comparator

JK FLIPFLOP

1 to 16 DEMUX

Octal to Binary Encoder

MOD 12 COUNTER

Ripple carry Adder

1 to 16 DEMUX

SIPO

Ripple carry Adder

OR

CONSENSUS LAW 2

MUX with counter

16 to 1 mux

Ripple carry Adder

EXCESS-3 TO BCD

BCD TO EXCESS-3

16 to 1 mux

CONSENSUS LAW 2

4-bit parity Checker

CONSENSUS LAW 2

EXCESS-3 TO BCD

3 bit parity generator

4 bit parity generator

NAND USING 2 TO 1 MUX

SR FLIPFLOP

4 TO 16

ABSORPTION LAW 3

COMMUTATIVE LAW OF MULTIPLICATION

CONSENSUS THEROEM

2 x 1 ENCODER

ASSOCIATIVE LAW OF ADDITION

SR FLIPFLOP

NOR

NAND

DISTRIBUTIVE PROPERTY 2

NOR

TFF

T FLIPFLOP

ASSOCIATIVE LAW OF MULTIPLICATION

MOD 12 COUNTER

IMPLEMENTION USING MUX(2)

IMPLEMENTATION USING MUX(1)

IMPLEMENTATION USING MUX(1)

2 to 4 Decoder

16 to 1 mux

DFF USING JKFF

FULL SUBTRACTOR

HALF SUBTRACTOR

CONSENSUS LAW 2

8 to 1 MUX

AND USING 2 TO 1 MUX

1 to 2 DEMUX

8 TO 3 PRIORITY ENCODER

2 x 1 ENCODER

AND USING 2 TO 1 MUX

4 TO 16

1 to 2 DEMUX

4 bit synchronous down counter

D FLIPFLOP

CONSENSUS LAW 2

JKFF USING DFF

NAND gate

XNOR gate

Ripple carry Adder

Half adder using minimal number of NAND gates

NOR BASED SR FLIPFLOP

32 to 1 MUX using 4 to 1 MUX

4 bit parity checker

NOT USING 2 TO 1 MUX

2 bit Magnitude Comparator

4 TO 16

24 to 1 MUX using 8 to 1 MUX

2 to 1 MUX

2 x 1 ENCODER

1 bit Magnitude Comparator

4 TO 16

4 TO 16

NOT

AND

1 to 2 DEMUX

NOR BASED SR FLIPFLOP

JKFF USING DFF

TFF

D FLIPFLOP

FULL SUBTRACTOR

4 bit synchronous counter

CONSENSUS LAW 2

4 BIT ADDER /SUBTRACTOR

EXOR

AND USING 2 TO 1 MUX

4 to 2 priority encoder

4 bit synchronous counter

AND gate

DISTRIBUTIVE PROPERTY

4 bit synchronous UP/DOWN counter

FULL ADDER USING TWO HALF ADDERS

4 bit synchronous UP/DOWN counter

COMMUTATIVE LAW OF ADDITION

MOD 7 COUNTER

TFF USING DFF

4 bit ripple counter

HALF SUBTRACTOR

FULL ADDER-NAND NAND IMPLEMENTATION

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

GRAY TO BINARY CODE CONVERTER

BCD ADDER

OR USING 2 TO 1 MUX

MOD 7 COUNTER

CONSENSUS LAW 2

RIPPLE CARRY SUBTRACTOR

FULL SUBRACTOR USING NOR GATES

ASSOCIATIVE LAW OF MULTIPLICATION

Ripple carry Adder

SR FLIPFLOP

IMPLEMENTION USING MUX(2)

Demorgans theorem-I

NAND BASED SR FLIPFLOP

4 bit ripple counter

SISO

ABSORPTION LAW 2

ABSORPTION LAW 1

3 bit binary counter

SISO

SISO

EX NOR

D FLIPFLOP

D FLIPFLOP

4 bit ripple down counter

4 bit bidirectional shift register

Full adder

4 bit ripple counter

IMPLEMENTION USING MUX(2)

Ripple carry Adder

3 bit Parity Checker

MOD 12 COUNTER

MOD 7 COUNTER

4 bit ripple counter

4 bit ripple counter with decoded outputs

MOD 12 COUNTER

1 to 16 DEMUX

8 TO 3 PRIORITY ENCODER

Verification of Boolean postulates and laws

Verification of Boolean postulates and laws

MOD 12 COUNTER

AND USING 2 TO 1 MUX

4 bit synchronous counter

4-bit parity Checker

FULL SUBTRACTOR

NOT gate

16 to 1 mux

2 to 4 Decoder

FULL ADDER USING BASIC GATES

4 x 2 ENCODER

BCD to 7 segment decoder

Octal to Binary Encoder

1 to 16 DEMUX

AND USING 2 TO 1 MUX

Ripple carry Adder

CONSENSUS LAW 2

1 x 2 DECODER

2 to 4 Decoder

2 to 4 Decoder

PISO

4 x 2 ENCODER

16 to 1 mux

TFF USING SRFF

IMPLEMENTION USING MUX(2)

4 to 2 priority encoder

DFF USING SRFF

DFF USING JKFF

Demorgans theprem-II

RIPPLE CARRY SUBTRACTOR

MOD 7 COUNTER

Ripple carry Adder

2 to 4 Decoder

Boolean potulates and laws

BCD ADDER

4 x 2 ENCODER

16 to 1 mux

OR USING 2 TO 1 MUX

DE MORGANS THEORM 2

8 to 1 MUX

BCD to Decimal Decoder

AND USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX

HALF ADDER USING BASIC GATES

1 to 16 DEMUX

HALF ADDER-NAND NAND IMPLEMENTATION

Octal to Binary Encoder

1 to 16 DEMUX

4 bit synchronous down counter

MUX with counter

Hlaf adder

Full adder using 2 hald adders

Demorgans theorem-I

BCD to Decimal Decoder

Decimal to BCD Encoder

Verification of Boolean postulates and laws

HALF ADDER USING MINIMAL NUMBER OF NAND GATES

4 bit synchronous down counter

BCD to Decimal Decoder

1 to 2 DEMUX

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

TFF USING DFF

JKFF using SRFF

SRFF USING TFF

AND gate

Ripple carry Adder

Ripple carry Adder

SRFF using DFF

16 to 1 mux

16 to 1 mux

Ripple carry Adder

MOD 12 COUNTER

Ripple carry Adder

HALF ADDER-NOR NOR GATES

mod-6 unit distance counter

Half adder using basic gates

counter having the states 0-2--4-7-0

TFF USING JKFF

AND USING 2 TO 1 MUX

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

3 bit binary counter

SR FLIPFLOP

4 bit ripple counter

4 BIT UP-DOWN COUNTER

RIPPLE CARRY SUBTRACTOR

2 x 4 DECODER

PIPO

SRFF USING JKFF

IMPLEMENTION USING MUX(2)

Ripple carry Adder

Ripple carry Adder

16 to 1 mux

AND USING 2 TO 1 MUX

counter that counts 0,2,4,7,0

4 bit ripple down counter

CONSENSUS LAW 2

OR USING 2 TO 1 MUX

4 bit synchronous down counter

1 to 2 DEMUX

AND USING 2 TO 1 MUX

1 to 16 DEMUX

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

3 x 8 DECODER

NOR BASED SR FLIPFLOP

4 bit synchronous down counter

1 to 2 DEMUX

FULL ADDER USING NOR GATES

8 to 1 MUX

Ripple carry Adder

JKFF Using TFF

OR gate

1 bit Magnitude Comparator

2 to 4 Decoder

1 to 16 DEMUX

8 TO 3 PRIORITY ENCODER

JK FLIPFLOP

DFF USING TFF

1 to 4 DEMUX

BCD TO EXCESS-3

counter that counts 0,2,4,7,0

1 to 8 DEMUX

1 to 8 DEMUX

2 x 1 ENCODER

2 to 4 Decoder

IMPLEMENTATION USING MUX(1)

3 BIT PARALLEL MULTIPLIER

3 bit binary counter

SR FLIPFLOP

MOD 12 COUNTER

HALF ADDER USING BASIC GATES

BINARY TO GRAY CODE CONVERTER

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

BCD ADDER

4 bit synchronous down counter

VERFICATION OF BOOLEAN LAWS AND POSTULATES

4 bit ripple down counter

8 TO 3 PRIORITY ENCODER

DFF USING JKFF

4 bit synchronous UP/DOWN counter

4 bit synchronous down counter

4 bit synchronous counter

DE MORGANS THEORM 1

BCD ADDER

RIPPLE CARRY SUBTRACTOR

CONSENSUS THEROEM

mod-6 unit distance counter

4 bit synchronous counter

3 bit binary counter

4 bit bidirectional shift register

NOR BASED SR FLIPFLOP

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

2 to 4 Decoder

4 bit synchronous down counter

ABSORPTION LAW 4

HALF SUBTRACTOR-NAND NAND IMPLEMENTATION

NAND BASED SR FLIPFLOP

Half subtractor using basic gates

IMPLEMENTION USING MUX(2)

2 x 1 ENCODER

NOR gate

3 bit Parity Checker

BCD to Decimal Decoder

Full subtractor using basic gates

Ripple carry Adder

JKFF Using TFF

4 bit synchronous down counter

1 to 16 DEMUX

1 to 2 DEMUX

NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX

32 to 1 MUX using 4 to 1 MUX

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

JK FLIPFLOP

4 x 2 ENCODER

4 x 2 ENCODER

IMPLEMENTATION USING MUX(1)

implementation of full adder using counter

implementation of full adder with mux and counter

4 to 1 MUX

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

EX-OR gate

4 bit ripple counter with decoded outputs

BCD to Decimal Decoder

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

MOD 12 COUNTER

Verification of Boolean postulates and laws

4 bit synchronous counter with ripple carry

2 x 1 ENCODER

FULL SUBRACTOR USING TWO HALF SUBTRACTOR

4 BIT UNIVERSAL SHIFT REGISTER

sequence generator using counter

BINARY TO GRAY CODE CONVERTER

4 bit ripple down counter

HALF ADDER USING MINIMAL NUMBER OF NAND GATES

4 bit ripple counter

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

4 bit ripple counter with decoded outputs

32 to 1 MUX using 4 to 1 MUX

JK FLIPFLOP