BCD to 7 segment decoder

MOD 12 COUNTER

MUX with counter

2 x 4 DECODER

2 to 4 Decoder

3-bit parity Checker

NOR BASED SR FLIPFLOP

TFF USING SRFF

HALF SUBTRACTOR

1 to 16 DEMUX

FULL ADDER

sequence generator using counter

FULL SUBTRACTOR-NAND NAND IMPLEMENTATION

GRAY TO BINARY CODE CONVERTER

PISO

8 to 1 MUX

32 to 1 MUX using 4 to 1 MUX

OR USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX

MOD 12 COUNTER

HALF ADDER USING MINIMAL NUMBER OF NAND GATES

IMPLEMENTION USING MUX(2)

NOR USING 2 TO 1 MUX

EXCESS-3 TO BCD

ABSORPTION LAW 1

BCD TO EXCESS-3

AND

FULL SUBRACTOR USING TWO HALF SUBTRACTOR

Untitled

DFF USING INBUILT

JK FF

D FLIPFLOP

TFF USING JKFF

COMMUTATIVE LAW OF MULTIPLICATION

ABSORPTION LAW 2

ABSORPTION LAW 3

DISTRIBUTIVE PROPERTY 2

DE MORGANS THEORM 2

4 BIT SYNCHRONOUS UP COUNTER

HALF SUBTRACTOR-NOR NOR IMPLEMENTATION

NAND

NOR

AND

EX NOR

NOT

EXOR

HALF ADDER

DISTRIBUTIVE PROPERTY

1 x 2 DECODER

2 x 1 ENCODER

16 to 1 MUX

JK FLIPFLOP

JKFF Using TFF

MOD 7 COUNTER

HALF SUBTRACTOR USING BASIC GATES

TFF

FULL ADDER-NAND NAND IMPLEMENTATION

1 to 8 DEMUX

4 bit bidirectional shift register

16 to 1 MUX

CONSENSUS THEROEM

FULL SUBRACTOR USING NOR GATES

4 x 2 ENCODER

SRFF using DFF

JKFF USING DFF

JKFF using SRFF

SRFF USING TFF

SRFF USING JKFF

ABSORPTION LAW 4

1 to 2 DEMUX

4 bit parity generator

2 bit Magnitude Comparator

1 to 4 DEMUX

HALF ADDER USING BASIC GATES

HALF ADDER-NAND NAND IMPLEMENTATION

Octal to Binary Encoder

Decimal to BCD Encoder

FULL ADDER USING TWO HALF ADDERS

24 to 1 MUX using 8 to 1 MUX

implementation of full adder with mux and counter

HALF ADDER-NOR NOR IMPLEMENTATION

AND USING 2 TO 1 MUX

DE MORGANS THEORM 1

TFF USING DFF

4 bit synchronous UP/DOWN counter

4 bit synchronous down counter

SISO

2 to 4 Decoder

4 bit ripple down counter

ASSOCIATIVE LAW OF ADDITION

FULL SUBRACTOR USING BASIC GATES

mod-6 unit distance counter

SIPO

VERFICATION OF BOOLEAN LAWS AND POSTULATES

MOD 7 COUNTER

DFF USING JKFF

PIPO

NAND BASED SR FLIPFLOP

AND

lab

COMMUTATIVE LAW OF ADDITION

1 bit Magnitude Comparator

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

1 bit Magnitude Comparator

4 bit ripple counter

EXOR USING 2 TO 1 MUX

4 BIT UP-DOWN COUNTER

implementation of full adder using counter

DFF USING TFF

counter that counts 0,2,4,7,0

4 bit parity checker

8 TO 3 PRIORITY ENCODER

DFF USING SRFF

3 x 8 DECODER

4 bit ripple counter with decoded outputs

4 to 2 priority encoder

3 bit binary counter

ASSOCIATIVE LAW OF MULTIPLICATION

4 to 1 MUX

IMPLEMENTATION USING MUX(1)

16 to 1 MUX

4 BIT UNIVERSAL SHIFT REGISTER

3 bit Parity Checker

3 bit parity generator

BCD to Decimal Decoder

16 to 1 MUX

4 TO 16

4 bit synchronous counter

FULL SUBTRACTOR

2 to 1 MUX

FULL ADDER USING NOR GATES

OR

BINARY TO GRAY CODE CONVERTER

HALF SUBTRACTOR-NAND NAND IMPLEMENTATION

4 bit synchronous counter with ripple carry

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

FULL ADDER USING BASIC GATES

SR FLIPFLOP