NIKITA GAUTAM
Member since: 3 years
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Experiment-14-a
Experiment-14-a
Public
EXP 14 b
EXP 14 b
Public
Experiment-16
Experiment-16
Public
Exp-17(universal register)
Exp-17(universal register)
Public
Experiment.5b
Experiment.5b
Public
EXPERIMENT-7(8*2)
EXPERIMENT-7(8*2)
Public
EXPERIMENT-8(2 *4 decoder)
EXPERIMENT-8(2 *4 decoder)
Public
Experiment 8-(3to8decoder)
Experiment 8-(3to8decoder)
Public
EXPERIMENT-9B
EXPERIMENT-9B
Public
EXPERIMENT-9
EXPERIMENT-9
Public
experiment-10
experiment-10
Public
experiment-10
experiment-10
Public
Experiment-12
Experiment-12
Public
JK flipflop
JK flipflop
Public
exp-11(SR latch NAND and OR)
exp-11(SR latch NAND and OR)
Public
Clocked SR using NAND
Clocked SR using NAND
Public
Untitled
Untitled
Public
Experiment-14-b
Experiment-14-b
Public
D latch using NOR
D latch using NOR
Public
EXPERMINENT-15
EXPERMINENT-15
Public
Exp-17 shift left using D
Exp-17 shift left using D
Public
internal-half and full subtractor
internal-half and full subtractor
Public
full subtractor
full subtractor
Public
Half subtactor
Half subtactor
Public
Experiment-6b
Experiment-6b
Public
Experiment -7(4*2)
Experiment -7(4*2)
Public
Master slave d flipflop
Master slave d flipflop
Public
left shift using jk
left shift using jk
Public
EXPERIMENT 1
EXPERIMENT 1
Public
FULL ADDER
FULL ADDER
Public
exp.5
exp.5
Public
Experiment -6
Experiment -6
Public
EXPERIMENT.4
EXPERIMENT.4
Public
EXPERIMENT-15B
EXPERIMENT-15B
Public
Exp-17(shift right using D)
Exp-17(shift right using D)
Public
internal-half adder and full adder
internal-half adder and full adder
Public
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