project.name

Jeyadesh J

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

Synchronous counte

Synchronous counte
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magnitude comparator

magnitude comparator
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Design of asynchronous Counter

Design of asynchronous Counter
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Digital Model Lab

Digital Model Lab
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Subtractor

Subtractor
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ASYNCHRONOUS COUNTER

ASYNCHRONOUS COUNTER
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De Morgan Theorem

De Morgan Theorem
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Binary to gray

Binary to gray
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Pairity

Pairity
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BCD

BCD
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bool

bool
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Logic Gates

Logic Gates
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Untitled

Untitled
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Untitled

Untitled
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Associative Law

Associative Law
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half adder

half adder
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bool

bool
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Gray to Binary

Gray to Binary
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Commutative law

Commutative law
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serial in out

serial in out
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PARALLEL ADDER/SUBTRACTOR

PARALLEL ADDER/SUBTRACTOR
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Full adder using multiplexer

Full adder using multiplexer
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Jeyadesh J is not a collaborator of any project.

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