project.name

abhishek tyagi

Member since: 4 years

Educational Institution: KIET GROUP OF INSTITUTIONS

Country: India

MULTIPLEXER

MULTIPLEXER
Public
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Edge triggered FF

Edge triggered FF
Public
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2 bit arithmetic logic unit

2 bit arithmetic logic unit
Public
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1 x 16 Demultiplexer [email protected]

1 x 16 Demultiplexer [email protected]
Public
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EXP 6 MULTIPLIER 2 X 2 ABHISHEK TYAGI 1923IT1200

EXP 6 MULTIPLIER 2 X 2 ABHISHEK TYAGI 1923IT1200
Public
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4*1mux

4*1mux
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2 TO 4 DECODER EXP 8 ABHISHEK TYAGI

2 TO 4 DECODER EXP 8 ABHISHEK TYAGI
Public
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2 x 4 decoder circuit

2 x 4 decoder circuit
Public
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EXP 3

EXP 3
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full adder

full adder
Public
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exp 15 arithmetic logic unit

exp 15 arithmetic logic unit
Public
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Demux

Demux
Public
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NOR Latch Abhishek tyagi exp 11

NOR Latch Abhishek tyagi exp 11
Public
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2 x 4 decoder circuit

2 x 4 decoder circuit
Public
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EXP 14 ABHISHEK TYAGI

EXP 14 ABHISHEK TYAGI
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EXP 16 Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s

EXP 16 Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Public
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8 to 3 encoder

8 to 3 encoder
Public
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Untitled

Untitled
Public
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Jk flip flop exp 12 abhishek tyagi

Jk flip flop exp 12 abhishek tyagi
Public
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basic gates

basic gates
Public
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Logic Gates

Logic Gates
Public
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1 x 4 Demultiplexers

1 x 4 Demultiplexers
Public
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Exp 17 shift register JK flip flop

Exp 17 shift register JK flip flop
Public
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basic gates

basic gates
Public
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3 bits carry ahead adder

3 bits carry ahead adder
Public
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exp 15 arithmetic logic unit

exp 15 arithmetic logic unit
Public
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8 x 1 mux EXP 9 ABHISHEK TYAGI 1923IT1200

8 x 1 mux EXP 9 ABHISHEK TYAGI 1923IT1200
Public
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BINARY TO GRAY CODE

BINARY TO GRAY CODE
Public
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D FLIP FLOP USING NAND LATCH

D FLIP FLOP USING NAND LATCH
Public
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3 X 8 DECODER

3 X 8 DECODER
Public
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Jk flip flop exp 12 abhishek tyagi 1923IT1200

Jk flip flop exp 12 abhishek tyagi 1923IT1200
Public
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NOR Latch Abhishek tyagi exp 11

NOR Latch Abhishek tyagi exp 11
Public
project.name

Untitled

Untitled
Public
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EXP 16 Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s

EXP 16 Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Public
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EXP 6 MULTIPLIER 2 X 2 ABHISHEK TYAGI 1923IT1200

EXP 6 MULTIPLIER 2 X 2 ABHISHEK TYAGI 1923IT1200
Public
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EXP 7 (4 TO 2) ENCODER CIRCUIT ABHISHEK TYAGI1923IT1200

EXP 7 (4 TO 2) ENCODER CIRCUIT ABHISHEK TYAGI1923IT1200
Public
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Exp 6 (Multiplier 2x2)abhishek tyagi 1923it1200

Exp 6 (Multiplier 2x2)abhishek tyagi 1923it1200
Public
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Analysis and simulation of sequential circuit using D and JK flip flop

Analysis and simulation of sequential circuit using D and JK flip flop
Public
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4X2 ENCODER, 8X3 ENCODER ABHISHEK TYAGI 1923IT1200

4X2 ENCODER, 8X3 ENCODER ABHISHEK TYAGI 1923IT1200
Public
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Jk flip flop exp 12 abhishek tyagi

Jk flip flop exp 12 abhishek tyagi
Public
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Gray to binary code

Gray to binary code
Public
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Exp 6 (Multiplier 2x2)abhishek tyagi 1923it1200

Exp 6 (Multiplier 2x2)abhishek tyagi 1923it1200
Public
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2 bit arithmetic logic unit

2 bit arithmetic logic unit
Public
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3 Bits binary Adder

3 Bits binary Adder
Public
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3 bits carry look ahead adder

3 bits carry look ahead adder
Public
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basic gates

basic gates
Public
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No result image
abhishek tyagi is not a collaborator of any project.