3 BIT PARALLEL MULTIPLIER

BCD ADDER

4 BIT PARALLEL ADDER/SUBTRACTOR

4 BIT PARALLEL ADDER/SUBTRACTOR

BCD ADDER

BCD to 7 segment decoder

1 x 2 DECODER

2 x 4 DECODER

BCD to Decimal Decoder

synchronous up counter

4 bit synchronous down counter

4 BIT UP-DOWN COUNTER

4 bit Ripple Counter

PISO

4 bit bidirectional shift register

4 bit synchronous down counter

4 BIT UNIVERSAL SHIFT REGISTER

Binary to gray code 1

Gray to binary code

FULL ADDER USING NAND GATES

4 bit synchronous UP/DOWN counter

BCD ADDER

BCD ADDER

3 BIT PARALLEL MULTIPLIER

BCD ADDER

CONSENSUS THEOREM

FULL ADDER USING NOR GATES

AND USING 2 TO 1 MUX

FULL ADDER USING XOR GATES

IMPLEMENTATION USING MUX(1)

4 to 1 MUX

8 to 1 MUX

EXOR USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX

32 to 1 MUX using 4 to 1 MUX

16 to 1 MUX

NOR USING 2 TO 1 MUX

24 to 1 MUX using 8 to 1 MUX

OR USING 2 TO 1 MUX

1 to 2 DEMUX

1 to 8 DEMUX

1 to 16 DEMUX

4 BIT ADDER /SUBTRACTOR

Octal to Binary Encoder

RIPPLE CARRY SUBTRACTOR

Ripple carry Adder

BCD ADDER

BCD ADDER

BCD ADDER

BCD ADDER

BCD ADDER

BCD ADDER

Decimal to BCD Encoder

4 to 2 priority encoder

2 x 1 ENCODER

3 x 8 DECODER

D FLIPFLOP

SR FLIPFLOP

SRFF USING JKFF

TFF USING SRFF

TFF USING DFF

JKFF USING DFF

SRFF using DFF

JKFF using SRFF

SRFF USING JKFF

TFF USING JKFF

SRFF USING TFF

SRFF USING JKFF

JKFF Using TFF

MOD 12 COUNTER

4 bit ripple up down counter

32 to 1 MUX using 4 to 1 MUX

BCD ADDER

3 BIT PARALLEL MULTIPLIER

IMPLEMENTION USING MUX(2)

JK FLIPFLOP

XOR

4 x 2 ENCODER

3 bit binary counter

MOD 7 COUNTER

4 BIT RIPPLE DOWN COUNTER

counter that counts 0,2,4,7,0

mod-6 unit distance counter

SIPO

mod-6 unit distance counter

PIPO

SISO

implementation of full adder with mux and counter

SIPO

PIPO

SISO

4 BIT UNIVERSAL SHIFT REGISTER

NAND

AND

XNOR

NOR

1 bit magnitude Comparator

VERIFICATION OF BOOLEAN PROPERTY & LAW

VERIFICATION OF BOOLEAN PROPERTIES AND LAWS

VERIFICATION OF BOOLEAN PROPERTY AND LAWS

VERIFICATION OF BOOLEAN PROPERTIES AND LAWS

HALF ADDER USING NAND GATES

BCD ADDER

2 to 1 MUX

NAND USING 2 TO 1 MUX

NAND BASED SR FLIPFLOP

DFF USING SRFF

D FLIPFLOP

FULL SUBTRACTOR USING NOR GATES

FULL SUBTRACTOR USING BASIC GATES

1 to 4 DEMUX

4 BIT ADDER /SUBTRACTOR

2 to 4 Decoder

4 BIT UP-DOWN COUNTER

sequence generator using counter

implementation of full adder using counter

4 bit synchronous counter

implementation of full adder using counter

implementation of full adder using counter

T FLIPFLOP

T FF

4 bit ripple counter with decoded outputs

4 bit bidirectional shift register

CONSENSUS THEOREM

IMPLEMENTATION USING MUX(1)

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

OR

NOT

Excess-3 to BCD

VERIFICATION OF BOOLEAN PROPERTIES AND LAWS

Gray to binary

PISO

VERIFICATION PF BOOLEAN PROPERTIES AND LAWS

NOR BASED SR FLIPFLOP