jothilakshmi
Member since: 4 years
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4 to 16 decoder
4 to 16 decoder
synchronous counter
synchronous counter
bidirectional shift register
bidirectional shift register
4 bit bidirectional shift register
4 bit bidirectional shift register
Ripple carry Adder
Ripple carry Adder
JK FLIPFLOP
JK FLIPFLOP
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
3 x 8 DECODER
3 x 8 DECODER
1 x 2 DECODER
1 x 2 DECODER
2 x 4 DECODER
2 x 4 DECODER
1 x 2 DECODER
1 x 2 DECODER
Decimal to BCD Encoder
Decimal to BCD Encoder
4 BIT ADDER /SUBTRACTOR
4 BIT ADDER /SUBTRACTOR
4 bit adder/subtractor
4 bit adder/subtractor
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
BCD ADDER
BCD ADDER
1 to 16 DEMUX
1 to 16 DEMUX
Untitled
Untitled
Untitled
Untitled
Untitled
Untitled
Untitled
Untitled
Untitled
Untitled
3 TO 8 DECODER
3 TO 8 DECODER
t
t
BCD TO 7 SEGMENT DECODER
BCD TO 7 SEGMENT DECODER
4 TO 16
4 TO 16
4 TO 16
4 TO 16
4 TO 16
4 TO 16
4 TO 16
4 TO 16
BCD to Decimal Decoder
BCD to Decimal Decoder
24 to 1 MUX using 8 to 1 MUX
24 to 1 MUX using 8 to 1 MUX
2 to 1 MUX
2 to 1 MUX
Octal to Binary Encoder
Octal to Binary Encoder
EXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
1 to 16 DEMUX
1 to 16 DEMUX
1 to 16 DEMUX
1 to 16 DEMUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
TFF
TFF
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
synchronous up counter
synchronous up counter
implementation of full adder with mux and counter
implementation of full adder with mux and counter
TFF
TFF
DFF USING TFF
DFF USING TFF
TFF USING JKFF
TFF USING JKFF
TFF USING DFF
TFF USING DFF
JKFF Using TFF
JKFF Using TFF
SRFF USING TFF
SRFF USING TFF
JKFF using SRFF
JKFF using SRFF
JKFF USING DFF
JKFF USING DFF
SR FLIPFLOP
SR FLIPFLOP
DFF USING JKFF
DFF USING JKFF
TFF
TFF
JK FLIPFLOP
JK FLIPFLOP
TFF USING DFF
TFF USING DFF
DFF USING TFF
DFF USING TFF
SRFF using DFF
SRFF using DFF
JKFF using SRFF
JKFF using SRFF
SRFF USING JKFF
SRFF USING JKFF
SRFF using DFF
SRFF using DFF
JKFF USING DFF
JKFF USING DFF
SRFF USING TFF
SRFF USING TFF
SRFF using DFF
SRFF using DFF
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
D FLIPFLOP
JKFF Using TFF
JKFF Using TFF
JKFF Using TFF
JKFF Using TFF
4 bit Ripple Counter
4 bit Ripple Counter
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
JKFF USING DFF
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
NAND
NAND
NAND
NAND
NAND
NAND
D FLIPFLOP
D FLIPFLOP
IMPLEMENTATION USING MINTERM USING MUX
IMPLEMENTATION USING MINTERM USING MUX
Ripple carry Adder
Ripple carry Adder
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
MOD 12 COUNTER
MOD 12 COUNTER
2 to 1 MUX
2 to 1 MUX
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
JKFF USING DFF
JKFF USING DFF
JKFF Using TFF
JKFF Using TFF
1:8 DEMUX
1:8 DEMUX
4 bit synchronous down counter
4 bit synchronous down counter
CONSENSUS LAW 2
CONSENSUS LAW 2
4 BIT ADDER /SUBTRACTOR
4 BIT ADDER /SUBTRACTOR
1 to 2 DEMUX
1 to 2 DEMUX
Ripple carry Adder
Ripple carry Adder
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
BCD to Decimal Decoder
BCD to Decimal Decoder
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
implementation of full adder with mux and counter
implementation of full adder with mux and counter
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
implementation of full adder using counter
implementation of full adder using counter
MOD 7 COUNTER
MOD 7 COUNTER
Parallel in serial out
Parallel in serial out
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
EXCESS-3 TO BCD
EXCESS-3 TO BCD
GRAY TO BINARY CODE CONVERTER
GRAY TO BINARY CODE CONVERTER
BCD TO EXCESS-3
BCD TO EXCESS-3
Parallel in serial out
Parallel in serial out
4 bit synchronous counter
4 bit synchronous counter
4 bit synchronous counter
4 bit synchronous counter
4 bit synchronous counter
4 bit synchronous counter
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
SERIAL IN SERIAL OUT
SERIAL IN SERIAL OUT
parrallel in parallel out
parrallel in parallel out
SISO
SISO
SIPO
SIPO
4 bit Ripple Counter
4 bit Ripple Counter
4 bit Ripple Counter
4 bit Ripple Counter
4 bit Ripple Counter
4 bit Ripple Counter
SERIAL IN SERIAL OUT
SERIAL IN SERIAL OUT
4 bit bidirectional shift register
4 bit bidirectional shift register
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
JK FLIPFLOP
JK FLIPFLOP
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUX
16 to 1 MUX
16 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
2 to 1 MUX
4 to 16 decoder
4 to 16 decoder
16 to 1 mux
16 to 1 mux
Untitled
Untitled
4 to 16 decoder
4 to 16 decoder
Parallel in serial out
Parallel in serial out
1 to 16 DEMUX
1 to 16 DEMUX
CONSENSUS LAW 2
CONSENSUS LAW 2
Untitled
Untitled
CONSENSUS LAW 2
CONSENSUS LAW 2
Ripple carry Adder
Ripple carry Adder
1 to 8 DEMUX
1 to 8 DEMUX
MUX with counter
MUX with counter
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
Octal to Binary Encoder
Octal to Binary Encoder
synchronous up counter
synchronous up counter
NOR gate
NOR gate
NAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUX
4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN counter
NAND gate
NAND gate
OR gate
OR gate
EX-OR gate
EX-OR gate
AND gate
AND gate
VERIFICATION OF BOOLEAN POSTULATES AND LAWS
VERIFICATION OF BOOLEAN POSTULATES AND LAWS
VERIFICATION OF BOOLEAN POSTULATES AND LAWS
VERIFICATION OF BOOLEAN POSTULATES AND LAWS
consensus laws
consensus laws
OR USING 2 TO 1 MUX
OR USING 2 TO 1 MUX
4 TO 16
4 TO 16
4 to 2 priority encoder
4 to 2 priority encoder
2 x 4 DECODER
2 x 4 DECODER
4 to 1 mux
4 to 1 mux
8 to 1 MUX
8 to 1 MUX
4 x 2 ENCODER
4 x 2 ENCODER
4 to 2 priority encoder
4 to 2 priority encoder
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
2 x 1 ENCODER
2 x 1 ENCODER
1 to 16 DEMUX
1 to 16 DEMUX
8 to 1 MUX
8 to 1 MUX
Decimal to BCD Encoder
Decimal to BCD Encoder
2 x 4 DECODER
2 x 4 DECODER
SRFF using DFF
SRFF using DFF
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
1 to 4 DEMUX
1 to 4 DEMUX
synchronous up down counter
synchronous up down counter
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
TFF USING SRFF
TFF USING SRFF
16 to 1 MUX
16 to 1 MUX
16 to 1 MUX
16 to 1 MUX
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
TFF USING SRFF
TFF USING SRFF
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
4 BIT UP-DOWN COUNTER
4 BIT UP-DOWN COUNTER
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
ABSORPTION LAWS
ABSORPTION LAWS
8 to 1 MUX
8 to 1 MUX
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
BCD TO DECIMAL DECODER
BCD TO DECIMAL DECODER
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 to 1 MUX
4 to 1 MUX
T FLIPFLOP
T FLIPFLOP
DFF USING SRFF
DFF USING SRFF
SRFF USING JKFF
SRFF USING JKFF
DFF USING SRFF
DFF USING SRFF
TFF USING SRFF
TFF USING SRFF
8 to 1 MUX
8 to 1 MUX
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
JK FLIPFLOP
JK FLIPFLOP
JK FLIPFLOP
JK FLIPFLOP
JK FLIPFLOP
JK FLIPFLOP
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
4 bir adder/subtractor
4 bir adder/subtractor
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
T FLIPFLOP
T FLIPFLOP
TFF USING JKFF
TFF USING JKFF
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
4 BIT PARALLEL ADDER/SUBTRACTOR
4 BIT PARALLEL ADDER/SUBTRACTOR
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
SR FLIPFLOP
SR FLIPFLOP
DFF USING JKFF
DFF USING JKFF
AND USING 2 TO 1 MUX
AND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUX
16 to 1 mux
16 to 1 mux
4 BIT PARALLEL ADDER/SUBTRACTOR
4 BIT PARALLEL ADDER/SUBTRACTOR
implementation of full adder with mux and counter
implementation of full adder with mux and counter
4 to 1 MUX
4 to 1 MUX
D FLIPFLOP
D FLIPFLOP
JKFF USING DFF
JKFF USING DFF
Ripple carry Adder
Ripple carry Adder
BCD ADDER
BCD ADDER
3 bit binary counter
3 bit binary counter
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
4 bir adder/subtractor
4 bir adder/subtractor
CONSENSUS LAW 2
CONSENSUS LAW 2
JK FLIPFLOP
JK FLIPFLOP
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
CONSENSUS LAW 2
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
4 bit Ripple Counter
4 bit Ripple Counter
4 bit synchronous counter
4 bit synchronous counter
MOD 7 COUNTER
MOD 7 COUNTER
Octal to Binary Encoder
Octal to Binary Encoder
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
NOT
NOT
4 to 1 MUX
4 to 1 MUX
sequence generator using counter
sequence generator using counter
4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTER
MUX with counter
MUX with counter
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
BCD to Decimal Decoder
BCD to Decimal Decoder
BINARY TO GRAY CODE CONVERTER
BINARY TO GRAY CODE CONVERTER
T FLIPFLOP
T FLIPFLOP
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
NOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
MOD 7 COUNTER
MOD 7 COUNTER
implementation of full adder with mux and counter
implementation of full adder with mux and counter
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
2 x 1 ENCODER
2 x 1 ENCODER
Ripple carry Adder
Ripple carry Adder
Ripple carry Adder
Ripple carry Adder
Verification of truth table by using OR gate
Verification of truth table by using OR gate
4 to 2 priority encoder
4 to 2 priority encoder
counter having the states 0-2--4-7-0
counter having the states 0-2--4-7-0
1 to 16 DEMUX
1 to 16 DEMUX
implementation of full adder with mux and counter
implementation of full adder with mux and counter
4 bit synchronous down counter
4 bit synchronous down counter
implementation of full adder with mux and counter
implementation of full adder with mux and counter
4 to 2 priority encoder
4 to 2 priority encoder
implementation of full adder using counter
implementation of full adder using counter
4 bit bidirectional shift register
4 bit bidirectional shift register
1 to 8 DEMUX
1 to 8 DEMUX
Octal to Binary Encoder
Octal to Binary Encoder
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUX
Untitled
Untitled
CONSENSUS LAW 2
CONSENSUS LAW 2
4 BIT ADDER /SUBTRACTOR
4 BIT ADDER /SUBTRACTOR
Untitled
Untitled
parrallel in parallel out
parrallel in parallel out
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
NOT gate
NOT gate
mod-6 unit distance counter
mod-6 unit distance counter
NAND
NAND
CONSENSUS LAW 2
CONSENSUS LAW 2
implementation of full adder with mux and counter
implementation of full adder with mux and counter
implementation of full adder with mux and counter
implementation of full adder with mux and counter
4-bit bidirectional shift register
4-bit bidirectional shift register
AND USING 2 TO 1 MUX
AND USING 2 TO 1 MUX
EX-NOR gate
EX-NOR gate
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
AND gate
AND gate
implementation of full adder with mux and counter
implementation of full adder with mux and counter
IMPLEMENTION USING MUX(2)
IMPLEMENTION USING MUX(2)
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