project.name

jothilakshmi

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

4 to 16 decoder

4 to 16 decoder
Public
project.name

synchronous counter

synchronous counter
Public
project.name

bidirectional shift register

bidirectional shift register
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
Public
project.name

3 x 8 DECODER

3 x 8 DECODER
Public
project.name

1 x 2 DECODER

1 x 2 DECODER
Public
project.name

2 x 4 DECODER

2 x 4 DECODER
Public
project.name

1 x 2 DECODER

1 x 2 DECODER
Public
project.name

Decimal to BCD Encoder

Decimal to BCD Encoder
Public
project.name

NAND

NAND
Public
project.name

4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
Public
project.name

4 bit adder/subtractor

4 bit adder/subtractor
Public
project.name

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
Public
project.name

BCD ADDER

BCD ADDER
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

3 TO 8 DECODER

3 TO 8 DECODER
Public
project.name

t

t
Public
project.name

BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
Public
project.name

4 TO 16

4 TO 16
Public
project.name

4 TO 16

4 TO 16
Public
project.name

4 TO 16

4 TO 16
Public
project.name

4 TO 16

4 TO 16
Public
project.name

BCD to Decimal Decoder

BCD to Decimal Decoder
Public
project.name

24 to 1 MUX using 8 to 1 MUX

24 to 1 MUX using 8 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

Octal to Binary Encoder

Octal to Binary Encoder
Public
project.name

EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
Public
project.name

NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

TFF

TFF
Public
project.name

NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
Public
project.name

synchronous up counter

synchronous up counter
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

TFF

TFF
Public
project.name

DFF USING TFF

DFF USING TFF
Public
project.name

TFF USING JKFF

TFF USING JKFF
Public
project.name

TFF USING DFF

TFF USING DFF
Public
project.name

JKFF Using TFF

JKFF Using TFF
Public
project.name

SRFF USING TFF

SRFF USING TFF
Public
project.name

JKFF using SRFF

JKFF using SRFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

SR FLIPFLOP

SR FLIPFLOP
Public
project.name

DFF USING JKFF

DFF USING JKFF
Public
project.name

TFF

TFF
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

TFF USING DFF

TFF USING DFF
Public
project.name

DFF USING TFF

DFF USING TFF
Public
project.name

SRFF using DFF

SRFF using DFF
Public
project.name

JKFF using SRFF

JKFF using SRFF
Public
project.name

SRFF USING JKFF

SRFF USING JKFF
Public
project.name

SRFF using DFF

SRFF using DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

SRFF USING TFF

SRFF USING TFF
Public
project.name

SRFF using DFF

SRFF using DFF
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

JKFF Using TFF

JKFF Using TFF
Public
project.name

JKFF Using TFF

JKFF Using TFF
Public
project.name

4 bit Ripple Counter

4 bit Ripple Counter
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

4 BIT RIPPLE DOWN COUNTER

4 BIT RIPPLE DOWN COUNTER
Public
project.name

NAND

NAND
Public
project.name

NAND

NAND
Public
project.name

NAND

NAND
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

IMPLEMENTATION USING MINTERM USING MUX

IMPLEMENTATION USING MINTERM USING MUX
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
Public
project.name

MOD 12 COUNTER

MOD 12 COUNTER
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

JKFF USING DFF

JKFF USING DFF
Public
project.name

JKFF Using TFF

JKFF Using TFF
Public
project.name

1:8 DEMUX

1:8 DEMUX
Public
project.name

4 bit synchronous down counter

4 bit synchronous down counter
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
Public
project.name

1 to 2 DEMUX

1 to 2 DEMUX
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE

VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
Public
project.name

BCD to Decimal Decoder

BCD to Decimal Decoder
Public
project.name

counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
Public
project.name

32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
Public
project.name

implementation of full adder using counter

implementation of full adder using counter
Public
project.name

MOD 7 COUNTER

MOD 7 COUNTER
Public
project.name

Parallel in serial out

Parallel in serial out
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

EXCESS-3 TO BCD

EXCESS-3 TO BCD
Public
project.name

GRAY TO BINARY CODE CONVERTER

GRAY TO BINARY CODE CONVERTER
Public
project.name

BCD TO EXCESS-3

BCD TO EXCESS-3
Public
project.name

Parallel in serial out

Parallel in serial out
Public
project.name

4 bit synchronous counter

4 bit synchronous counter
Public
project.name

4 bit synchronous counter

4 bit synchronous counter
Public
project.name

4 bit synchronous counter

4 bit synchronous counter
Public
project.name

SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

SERIAL IN SERIAL OUT

SERIAL IN SERIAL OUT
Public
project.name

parrallel in parallel out

parrallel in parallel out
Public
project.name

SISO

SISO
Public
project.name

SIPO

SIPO
Public
project.name

4 bit Ripple Counter

4 bit Ripple Counter
Public
project.name

4 bit Ripple Counter

4 bit Ripple Counter
Public
project.name

4 bit Ripple Counter

4 bit Ripple Counter
Public
project.name

SERIAL IN SERIAL OUT

SERIAL IN SERIAL OUT
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

SERIAL IN PARALLEL OUT

SERIAL IN PARALLEL OUT
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

IMPLEMENTATION USING MINTERMS WITH MUX

IMPLEMENTATION USING MINTERMS WITH MUX
Public
project.name

16 to 1 MUX

16 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

2 to 1 MUX

2 to 1 MUX
Public
project.name

4 to 16 decoder

4 to 16 decoder
Public
project.name

16 to 1 mux

16 to 1 mux
Public
project.name

Untitled

Untitled
Public
project.name

4 to 16 decoder

4 to 16 decoder
Public
project.name

Parallel in serial out

Parallel in serial out
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

Untitled

Untitled
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

1 to 8 DEMUX

1 to 8 DEMUX
Public
project.name

MUX with counter

MUX with counter
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

Octal to Binary Encoder

Octal to Binary Encoder
Public
project.name

synchronous up counter

synchronous up counter
Public
project.name

NOR gate

NOR gate
Public
project.name

NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

NAND gate

NAND gate
Public
project.name

OR gate

OR gate
Public
project.name

EX-OR gate

EX-OR gate
Public
project.name

AND gate

AND gate
Public
project.name

VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
Public
project.name

VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
Public
project.name

consensus laws

consensus laws
Public
project.name

OR USING 2 TO 1 MUX

OR USING 2 TO 1 MUX
Public
project.name

4 TO 16

4 TO 16
Public
project.name

4 to 2 priority encoder

4 to 2 priority encoder
Public
project.name

2 x 4 DECODER

2 x 4 DECODER
Public
project.name

4 to 1 mux

4 to 1 mux
Public
project.name

8 to 1 MUX

8 to 1 MUX
Public
project.name

4 x 2 ENCODER

4 x 2 ENCODER
Public
project.name

4 to 2 priority encoder

4 to 2 priority encoder
Public
project.name

4 BIT RIPPLE DOWN COUNTER

4 BIT RIPPLE DOWN COUNTER
Public
project.name

2 x 1 ENCODER

2 x 1 ENCODER
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

8 to 1 MUX

8 to 1 MUX
Public
project.name

Decimal to BCD Encoder

Decimal to BCD Encoder
Public
project.name

2 x 4 DECODER

2 x 4 DECODER
Public
project.name

SRFF using DFF

SRFF using DFF
Public
project.name

4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
Public
project.name

VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE

VERIFICATION OF BOOLEAN POSTULATES AND LAWS ASSOCIATIVE
Public
project.name

1 to 4 DEMUX

1 to 4 DEMUX
Public
project.name

synchronous up down counter

synchronous up down counter
Public
project.name

4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
Public
project.name

3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
Public
project.name

TFF USING SRFF

TFF USING SRFF
Public
project.name

16 to 1 MUX

16 to 1 MUX
Public
project.name

16 to 1 MUX

16 to 1 MUX
Public
project.name

NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
Public
project.name

TFF USING SRFF

TFF USING SRFF
Public
project.name

NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
Public
project.name

4 BIT UP-DOWN COUNTER

4 BIT UP-DOWN COUNTER
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

ABSORPTION LAWS

ABSORPTION LAWS
Public
project.name

8 to 1 MUX

8 to 1 MUX
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

BCD TO DECIMAL DECODER

BCD TO DECIMAL DECODER
Public
project.name

32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
Public
project.name

8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
Public
project.name

4 to 1 MUX

4 to 1 MUX
Public
project.name

T FLIPFLOP

T FLIPFLOP
Public
project.name

DFF USING SRFF

DFF USING SRFF
Public
project.name

SRFF USING JKFF

SRFF USING JKFF
Public
project.name

DFF USING SRFF

DFF USING SRFF
Public
project.name

TFF USING SRFF

TFF USING SRFF
Public
project.name

8 to 1 MUX

8 to 1 MUX
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

4 bir adder/subtractor

4 bir adder/subtractor
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

T FLIPFLOP

T FLIPFLOP
Public
project.name

TFF USING JKFF

TFF USING JKFF
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

4 BIT PARALLEL ADDER/SUBTRACTOR

4 BIT PARALLEL ADDER/SUBTRACTOR
Public
project.name

NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
Public
project.name

SR FLIPFLOP

SR FLIPFLOP
Public
project.name

DFF USING JKFF

DFF USING JKFF
Public
project.name

AND USING 2 TO 1 MUX

AND USING 2 TO 1 MUX
Public
project.name

NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
Public
project.name

16 to 1 mux

16 to 1 mux
Public
project.name

4 BIT PARALLEL ADDER/SUBTRACTOR

4 BIT PARALLEL ADDER/SUBTRACTOR
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

4 to 1 MUX

4 to 1 MUX
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

BCD ADDER

BCD ADDER
Public
project.name

3 bit binary counter

3 bit binary counter
Public
project.name

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
Public
project.name

4 bir adder/subtractor

4 bir adder/subtractor
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

JK FLIPFLOP

JK FLIPFLOP
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

IMPLEMENTION USING MUX(2)

IMPLEMENTION USING MUX(2)
Public
project.name

counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
Public
project.name

4 bit Ripple Counter

4 bit Ripple Counter
Public
project.name

4 bit synchronous counter

4 bit synchronous counter
Public
project.name

MOD 7 COUNTER

MOD 7 COUNTER
Public
project.name

Octal to Binary Encoder

Octal to Binary Encoder
Public
project.name

EX-NOR gate

EX-NOR gate
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

NOT

NOT
Public
project.name

4 to 1 MUX

4 to 1 MUX
Public
project.name

sequence generator using counter

sequence generator using counter
Public
project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
Public
project.name

MUX with counter

MUX with counter
Public
project.name

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
Public
project.name

BCD to Decimal Decoder

BCD to Decimal Decoder
Public
project.name

BINARY TO GRAY CODE CONVERTER

BINARY TO GRAY CODE CONVERTER
Public
project.name

T FLIPFLOP

T FLIPFLOP
Public
project.name

32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
Public
project.name

NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
Public
project.name

4 BIT RIPPLE DOWN COUNTER

4 BIT RIPPLE DOWN COUNTER
Public
project.name

MOD 7 COUNTER

MOD 7 COUNTER
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

2 x 1 ENCODER

2 x 1 ENCODER
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

Ripple carry Adder

Ripple carry Adder
Public
project.name

Verification of truth table by using OR gate

Verification of truth table by using OR gate
Public
project.name

4 to 2 priority encoder

4 to 2 priority encoder
Public
project.name

counter having the states 0-2--4-7-0

counter having the states 0-2--4-7-0
Public
project.name

1 to 16 DEMUX

1 to 16 DEMUX
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

4 bit synchronous down counter

4 bit synchronous down counter
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

4 to 2 priority encoder

4 to 2 priority encoder
Public
project.name

implementation of full adder using counter

implementation of full adder using counter
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

1 to 8 DEMUX

1 to 8 DEMUX
Public
project.name

Octal to Binary Encoder

Octal to Binary Encoder
Public
project.name

IMPLEMENTATION USING MINTERMS WITH MUX

IMPLEMENTATION USING MINTERMS WITH MUX
Public
project.name

Untitled

Untitled
Public
project.name

CONSENSUS LAW 2

CONSENSUS LAW 2
Public
project.name

4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
Public
project.name

Untitled

Untitled
Public
project.name

parrallel in parallel out

parrallel in parallel out
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

NOT gate

NOT gate
Public
project.name

mod-6 unit distance counter

mod-6 unit distance counter
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name

4-bit bidirectional shift register

4-bit bidirectional shift register
Public
project.name

AND USING 2 TO 1 MUX

AND USING 2 TO 1 MUX
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

AND gate

AND gate
Public
project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter
Public
project.name
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