project.name

B.Subarathna

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

Truth Table for binary to gray

Truth Table for binary to gray
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binary to gray code VIII

binary to gray code VIII
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NAND using 2X1 MUX

NAND using 2X1 MUX
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2 to 1 MUX

2 to 1 MUX
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OR using 2X1 MUX

OR using 2X1 MUX
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4X1 MUX

4X1 MUX
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JK FF using logic gates

JK FF using logic gates
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JK FlipFlop

JK FlipFlop
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SR FF

SR FF
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D Flip Flop

D Flip Flop
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D Flip Flop

D Flip Flop
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T FF

T FF
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TFF using DFF

TFF using DFF
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JKFF using DFF

JKFF using DFF
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JKFF using SRFF

JKFF using SRFF
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JKFF using TFF

JKFF using TFF
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Mod 12 counter

Mod 12 counter
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4 bit ripple down counter

4 bit ripple down counter
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EXOR gate

EXOR gate
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EX NOR gate

EX NOR gate
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FULL SUBTRACTOR USING NAND

FULL SUBTRACTOR USING NAND
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HALF ADDER USING BASIC GATES

HALF ADDER USING BASIC GATES
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SR FF using logic gates

SR FF using logic gates
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HALF SUBTRACTOR USING EXOR GATE

HALF SUBTRACTOR USING EXOR GATE
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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4 Bit Ripple Counter

4 Bit Ripple Counter
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TFF using SRFF

TFF using SRFF
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SRFF using DFF

SRFF using DFF
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OR gate

OR gate
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NAND gate

NAND gate
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NOT gate

NOT gate
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NOR gate

NOR gate
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TFF using JKFF

TFF using JKFF
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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24X1 using 8X1

24X1 using 8X1
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HALF SUBTRACTOR USING NAND

HALF SUBTRACTOR USING NAND
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FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
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FULL ADDER USING EXOR

FULL ADDER USING EXOR
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AND gate

AND gate
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HALF SUBTRACTOR USING NOR

HALF SUBTRACTOR USING NOR
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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D FF using logic gates

D FF using logic gates
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T FF using logic gates

T FF using logic gates
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32X1 using 4X1 MUX

32X1 using 4X1 MUX
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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CONSENSUS THEOREM

CONSENSUS THEOREM
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CONSENSUS THEOREM

CONSENSUS THEOREM
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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VERIFICATION OF BOOLEAN POSTULATES AND LAWS

VERIFICATION OF BOOLEAN POSTULATES AND LAWS
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1:4 Demux

1:4 Demux
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BCD to Decimal Decoder

BCD to Decimal Decoder
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1 : 16 Demux

1 : 16 Demux
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HALF ADDER USING EXOR

HALF ADDER USING EXOR
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Octal to Binary encoder

Octal to Binary encoder
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Decimal to BCD encoder

Decimal to BCD encoder
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4 to 2 priority encoder

4 to 2 priority encoder
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8 to 3 priority encoder

8 to 3 priority encoder
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3 to 8 decoder

3 to 8 decoder
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2 to 4 decoder

2 to 4 decoder
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1 to 2 decoder

1 to 2 decoder
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FULL SUBTRACTOR USING NOR

FULL SUBTRACTOR USING NOR
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BCD to 7 segment decoder

BCD to 7 segment decoder
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FULL ADDER USING NAND

FULL ADDER USING NAND
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FULL SUBTRACTOR USING BASIC GATES

FULL SUBTRACTOR USING BASIC GATES
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FULL ADDER USING NOR

FULL ADDER USING NOR
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FULL SUBTRACTOR USING EXOR

FULL SUBTRACTOR USING EXOR
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2X1 encoder

2X1 encoder
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JK FlipFlop

JK FlipFlop
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T FlipFlop

T FlipFlop
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DFF using SRFF

DFF using SRFF
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DFF using JKFF

DFF using JKFF
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HALF ADDER USING NAND GATE

HALF ADDER USING NAND GATE
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3 Bit parity generator

3 Bit parity generator
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bcd to excess-3

bcd to excess-3
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2 to 1 MUX

2 to 1 MUX
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3-bit parity checker

3-bit parity checker
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NOT using 2 to 1 MUX

NOT using 2 to 1 MUX
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NAND based SR FF

NAND based SR FF
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8X1 MUX

8X1 MUX
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Excess-3 to BCD

Excess-3 to BCD
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1:8 Demux

1:8 Demux
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4 X 2 encoder

4 X 2 encoder
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4 bit parity generator

4 bit parity generator
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4-bit ripple up/down counter

4-bit ripple up/down counter
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SR FF using logic gates

SR FF using logic gates
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4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
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SRFF using JKFF

SRFF using JKFF
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Truth table for bcd to excess -3converter

Truth table for bcd to excess -3converter
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NOR using 2X1 MUX

NOR using 2X1 MUX
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Untitled

Untitled
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2 bit magnitude comparator

2 bit magnitude comparator
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SRFF using TFF

SRFF using TFF
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4 to 16 decoder

4 to 16 decoder
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16X1 MUX

16X1 MUX
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Gray to Binary code VIII

Gray to Binary code VIII
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NOR based SR FF

NOR based SR FF
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1 bit magnitude comparator

1 bit magnitude comparator
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1 to 2 Demux

1 to 2 Demux
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HALF ADDER USING NOR GATE

HALF ADDER USING NOR GATE
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