project.name

J.SHRUTHI RANJANI

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

2 TO 1 MUX BY OR GATE

2 TO 1 MUX BY OR GATE
Public
project.name

8 T0 3 PRIORITY ENCODER

8 T0 3 PRIORITY ENCODER
Public
project.name

1 to 2 decoder

1 to 2 decoder
Public
project.name

parallel in serial out

parallel in serial out
Public
project.name

SR FLIPFLOP

SR FLIPFLOP
Public
project.name

SR FLIPFLOP

SR FLIPFLOP
Public
project.name

10.JKFF USING SRFF

10.JKFF USING SRFF
Public
project.name

T FLIPFLOP USING INBULIT

T FLIPFLOP USING INBULIT
Public
project.name

serial in parallel out

serial in parallel out
Public
project.name

5.TFF USING JKFF

5.TFF USING JKFF
Public
project.name

EXNOR

EXNOR
Public
project.name

sequence generator using counter

sequence generator using counter
Public
project.name

4 bit synchronous down counter

4 bit synchronous down counter
Public
project.name

4 bit ripple up counter

4 bit ripple up counter
Public
project.name

DFF USING SRFF

DFF USING SRFF
Public
project.name

BCD TO DECIMAL DECODER

BCD TO DECIMAL DECODER
Public
project.name

mod 12 counter

mod 12 counter
Public
project.name

NOT GATE

NOT GATE
Public
project.name

NOR GATE

NOR GATE
Public
project.name

32 to 1 mux using 4 to 1 mux

32 to 1 mux using 4 to 1 mux
Public
project.name

4 bit ripple down counter

4 bit ripple down counter
Public
project.name

6.TFF USING DFF

6.TFF USING DFF
Public
project.name

4 to 1 mux

4 to 1 mux
Public
project.name

4 bit ripple counter

4 bit ripple counter
Public
project.name

PIPO

PIPO
Public
project.name

serial in serial out

serial in serial out
Public
project.name

BCD TO EXCESS 3 COVERTOR

BCD TO EXCESS 3 COVERTOR
Public
project.name

Untitled

Untitled
Public
project.name

2 TO 1 MUX BY AND GATE

2 TO 1 MUX BY AND GATE
Public
project.name

2 TO 1 MUX BY NAND GATE

2 TO 1 MUX BY NAND GATE
Public
project.name

2 TO 1 MUX BY NOT GATE

2 TO 1 MUX BY NOT GATE
Public
project.name

2 TO 1 MUX BY NOR GATE

2 TO 1 MUX BY NOR GATE
Public
project.name

4 BIT PARITY CHECKER AND GENERATOR

4 BIT PARITY CHECKER AND GENERATOR
Public
project.name

16 to 1 mux

16 to 1 mux
Public
project.name

SISO

SISO
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

D FLIPFLOP

D FLIPFLOP
Public
project.name

SR FILPFLOP

SR FILPFLOP
Public
project.name

3 bit binary counter

3 bit binary counter
Public
project.name

MUX with counter

MUX with counter
Public
project.name

Untitled

Untitled
Public
project.name

4 bit binary to grey

4 bit binary to grey
Public
project.name

4 bit synchronous counter

4 bit synchronous counter
Public
project.name

2to1mux by exor gate

2to1mux by exor gate
Public
project.name

full adder using nand gate

full adder using nand gate
Public
project.name

1 BIT MAGNITUDE COMPARATOR

1 BIT MAGNITUDE COMPARATOR
Public
project.name

4 bit bidirectional shift register

4 bit bidirectional shift register
Public
project.name

4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
Public
project.name

Half Adder using basic gates

Half Adder using basic gates
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
Public
project.name

octal to binary encoder

octal to binary encoder
Public
project.name

2 to 4 decoder

2 to 4 decoder
Public
project.name

8.SRFF USING TFF

8.SRFF USING TFF
Public
project.name

half subtractor using nor gate

half subtractor using nor gate
Public
project.name

3.DFF USING TFF

3.DFF USING TFF
Public
project.name

11.JKFF USING DFF

11.JKFF USING DFF
Public
project.name

DFF USING JKFF

DFF USING JKFF
Public
project.name

9.SRFF USING DFF

9.SRFF USING DFF
Public
project.name

7.SRFF USING JKFF

7.SRFF USING JKFF
Public
project.name

16 t0 1 mux

16 t0 1 mux
Public
project.name

JK FIPFLOP USING INBUILT

JK FIPFLOP USING INBUILT
Public
project.name

4 bit ripple up/down counter

4 bit ripple up/down counter
Public
project.name

12.JKFF USING TFF

12.JKFF USING TFF
Public
project.name

DELAY FLIPFLOP USNG INBUILT

DELAY FLIPFLOP USNG INBUILT
Public
project.name

MOD 12 COUNTER

MOD 12 COUNTER
Public
project.name

8 TO 1 MUX

8 TO 1 MUX
Public
project.name

mod-6 unit distance counter

mod-6 unit distance counter
Public
project.name

DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
Public
project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
Public
project.name

MOD 7 COUNTER

MOD 7 COUNTER
Public
project.name

2 to 1 mux

2 to 1 mux
Public
project.name

IMPLEMENTATION OF MINTERMS BY 4 TO 1 MUX

IMPLEMENTATION OF MINTERMS BY 4 TO 1 MUX
Public
project.name

4 bit grey to binary code convertor

4 bit grey to binary code convertor
Public
project.name

4 bit ripple down counter

4 bit ripple down counter
Public
project.name

4 BIT EXCESS 3 TO BCD

4 BIT EXCESS 3 TO BCD
Public
project.name

4.TFF USING SRFF

4.TFF USING SRFF
Public
project.name

counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
Public
project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

4 TO 2 PRIORITY ENCODER

4 TO 2 PRIORITY ENCODER
Public
project.name

Untitled

Untitled
Public
project.name

2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
Public
project.name

1 TO 8 DEMUX

1 TO 8 DEMUX
Public
project.name

RING COUNTER

RING COUNTER
Public
project.name

4 BIT PARITY GENERATOR AND CHECKER

4 BIT PARITY GENERATOR AND CHECKER
Public
project.name

BCD TO 7 SEGMENT DECODER

BCD TO 7 SEGMENT DECODER
Public
project.name

UNIVERSAL SHIFT REGISTER

UNIVERSAL SHIFT REGISTER
Public
project.name

T FLIPFLOP USING LOGIC GATES

T FLIPFLOP USING LOGIC GATES
Public
project.name

2 TO 4 DECODER

2 TO 4 DECODER
Public
project.name

implementation using minterms with2:1 mux

implementation using minterms with2:1 mux
Public
project.name

FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
Public
project.name

24 to 1 mux using 8 to 1 mux

24 to 1 mux using 8 to 1 mux
Public
project.name

implementation using minterms with 16:1 mux

implementation using minterms with 16:1 mux
Public
project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
Public
project.name

JACK KILBY FLIPFLOP USING LOGICGATES

JACK KILBY FLIPFLOP USING LOGICGATES
Public
project.name
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