p.kalavathi
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bidirectional shift register
bidirectional shift register
4 BIT RIPPLE COUNTER
4 BIT RIPPLE COUNTER
MOD 12 COUNTER
MOD 12 COUNTER
BINARY TO GRAY CODE
BINARY TO GRAY CODE
Ripple carry Adder
Ripple carry Adder
JK FLIPFLOP
JK FLIPFLOP
TFF
TFF
JK FLIPFLOP
JK FLIPFLOP
DFF USING JKFF
DFF USING JKFF
DFF USING SRFF
DFF USING SRFF
JKFF USING DFF
JKFF USING DFF
SRFF USING JKFF
SRFF USING JKFF
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
implementation of full adder with mux and counter
implementation of full adder with mux and counter
4 BIT RIPPLE COUNTER
4 BIT RIPPLE COUNTER
JKFF Using TFF
JKFF Using TFF
verification of Boolean postulates 1
verification of Boolean postulates 1
NOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX
32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUX
RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIER
Octal to Binary Encoder
Octal to Binary Encoder
AND USING 2 TO 1 MUX
AND USING 2 TO 1 MUX
4 bit synchronous counter
4 bit synchronous counter
GRAY TO BINARY CODE 1
GRAY TO BINARY CODE 1
4 to 2 priority encoder
4 to 2 priority encoder
parrallel in parallel out
parrallel in parallel out
SERIAL IN SERIAL OUT
SERIAL IN SERIAL OUT
implementation of full adder using counter
implementation of full adder using counter
sequence generator using counter
sequence generator using counter
4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTER
counter having the states 0-2--4-7-0
counter having the states 0-2--4-7-0
3 bit binary counter
3 bit binary counter
SISO
SISO
SIPO
SIPO
(AB)'=A'+B'
(AB)'=A'+B'
(A+B)'=A'B'
(A+B)'=A'B'
Boolean rules
Boolean rules
4 to 16 decoder
4 to 16 decoder
NOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUX
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERM USING MUX
IMPLEMENTATION USING MINTERM USING MUX
1 to 8 DEMUX
1 to 8 DEMUX
1 to 16 DEMUX
1 to 16 DEMUX
16 to 1 MUX
16 to 1 MUX
EXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUX
AND gate
AND gate
AND gate
AND gate
NOT gate
NOT gate
NOR
NOR
4 x 2 ENCODER
4 x 2 ENCODER
2 x 1 ENCODER
2 x 1 ENCODER
BCD to Decimal Decoder
BCD to Decimal Decoder
BCD TO 7 SEGMENT DECODER
BCD TO 7 SEGMENT DECODER
4 to 16 decoder
4 to 16 decoder
24 to 1 MUX using 8 to 1 MUX
24 to 1 MUX using 8 to 1 MUX
NAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUX
SERIAL IN PARALLEL OUT
SERIAL IN PARALLEL OUT
1 to 4 DEMUX
1 to 4 DEMUX
DISTRIBUTIVE PROPERTY
DISTRIBUTIVE PROPERTY
CONSENSUS THEOREM
CONSENSUS THEOREM
Decimal to BCD Encoder
Decimal to BCD Encoder
BCD ADDER
BCD ADDER
2 x 4 DECODER
2 x 4 DECODER
NOR BASED SR FLIPFLOP
NOR BASED SR FLIPFLOP
SR FLIPFLOP
SR FLIPFLOP
TFF USING JKFF
TFF USING JKFF
T FLIPFLOP
T FLIPFLOP
4 bit ripple counter with decoded outputs
4 bit ripple counter with decoded outputs
4-BIT RIPPLE UP/DOWN COUNTER
4-BIT RIPPLE UP/DOWN COUNTER
synchronous up counter
synchronous up counter
4 bit synchronous down counter
4 bit synchronous down counter
1 x 2 DECODER
1 x 2 DECODER
MOD 7 COUNTER
MOD 7 COUNTER
DFF USING TFF
DFF USING TFF
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
Untitled
Untitled
counter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0
SRFF using DFF
SRFF using DFF
SRFF USING TFF
SRFF USING TFF
TFF USING DFF
TFF USING DFF
JKFF using SRFF
JKFF using SRFF
OR gate
OR gate
GRAY TO BINARY CODE
GRAY TO BINARY CODE
Demorgon's theorem 1
Demorgon's theorem 1
8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
synchronous up down counter
synchronous up down counter
TFF USING SRFF
TFF USING SRFF
DFF USING TFF
DFF USING TFF
D FLIPFLOP
D FLIPFLOP
4 BIT ADDER /SUBTRACTOR
4 BIT ADDER /SUBTRACTOR
mod-6 unit distance counter
mod-6 unit distance counter
SRFF using DFF
SRFF using DFF
Ripple carry Adder
Ripple carry Adder
3 x 8 DECODER
3 x 8 DECODER
VERIFICATION OF BOOLEAN THEOREM 2
VERIFICATION OF BOOLEAN THEOREM 2
NAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOP
1 to 2 DEMUX
1 to 2 DEMUX
Parallel in serial out
Parallel in serial out
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