project.name

J.Jefina Miralin

Member since: 4 years

Educational Institution: Not Entered

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IMPLEMENTATION OF FULL ADDER WITH MUX AND COUNTER

IMPLEMENTATION OF FULL ADDER WITH MUX AND COUNTER
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PISO

PISO
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4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
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SR FLIPFLOP

SR FLIPFLOP
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D FLIPFLOP

D FLIPFLOP
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T FLIPFLOP

T FLIPFLOP
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DFF USING SRFF

DFF USING SRFF
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TFF

TFF
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DFF USING TFF

DFF USING TFF
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JKFF USING DFF

JKFF USING DFF
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JKFF Using TFF

JKFF Using TFF
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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
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implementation of full adder using counter

implementation of full adder using counter
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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mod-6 unit distance counter

mod-6 unit distance counter
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3 bit binary counter

3 bit binary counter
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4 bit synchronous counter

4 bit synchronous counter
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4 bit synchronous down counter

4 bit synchronous down counter
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4 bit synchronous down counter

4 bit synchronous down counter
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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4 BIT SYNCHRONOUS COUNTER

4 BIT SYNCHRONOUS COUNTER
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4 bit synchronous counter

4 bit synchronous counter
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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SIPO

SIPO
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4 BIT BIDIRECTIONAL SHIFT REGISTER

4 BIT BIDIRECTIONAL SHIFT REGISTER
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SISO

SISO
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4 bit bidirectional shift register

4 bit bidirectional shift register
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SISO

SISO
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PIPO

PIPO
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SIPO

SIPO
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PIPO

PIPO
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mod 12 counter

mod 12 counter
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mod 7 counter

mod 7 counter
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mod 7 counter

mod 7 counter
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1 TO 16 DEMUX

1 TO 16 DEMUX
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16 TO 1 MUX

16 TO 1 MUX
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32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX
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TFF USING JKFF

TFF USING JKFF
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JKFF using SRFF

JKFF using SRFF
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16 TO 1 MUX

16 TO 1 MUX
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JK FLIPFLOP

JK FLIPFLOP
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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SRFF using DFF

SRFF using DFF
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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project.name
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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project.name
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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project.name
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SRFF USING JKFF

SRFF USING JKFF
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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16 TO 1 MUX

16 TO 1 MUX
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PISO

PISO
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TFF USING DFF

TFF USING DFF
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JK FLIPFLOP

JK FLIPFLOP
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SRFF USING TFF

SRFF USING TFF
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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4 TO 1 MUX

4 TO 1 MUX
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sequence generator using counter

sequence generator using counter
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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project.name
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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4 bit synchronous counter

4 bit synchronous counter
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TFF USING SRFF

TFF USING SRFF
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DFF USING JKFF

DFF USING JKFF
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J.Jefina Miralin is not a collaborator of any project.

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