J.Jefina Miralin - Circuits

J.Jefina Miralin

Member since: 3 years

Educational Institution: Not Entered

Country: Not Entered

IMPLEMENTATION OF FULL ADDER WITH MUX AND COUNTER

IMPLEMENTATION OF FULL ADDER WITH MUX AND COUNTER

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project.name

4 bit synchronous counter

4 bit synchronous counter

Public

project.name

PISO

PISO

Public

project.name

4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR

Public

project.name

32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX

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SR FLIPFLOP

SR FLIPFLOP

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D FLIPFLOP

D FLIPFLOP

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T FLIPFLOP

T FLIPFLOP

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DFF USING SRFF

DFF USING SRFF

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TFF

TFF

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DFF USING TFF

DFF USING TFF

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JKFF USING DFF

JKFF USING DFF

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project.name

TFF USING SRFF

TFF USING SRFF

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JKFF Using TFF

JKFF Using TFF

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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

implementation of full adder using counter

implementation of full adder using counter

Public

project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER

Public

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sequence generator using counter

sequence generator using counter

Public

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mod-6 unit distance counter

mod-6 unit distance counter

Public

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3 bit binary counter

3 bit binary counter

Public

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4 bit synchronous counter

4 bit synchronous counter

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

4 bit synchronous down counter

4 bit synchronous down counter

Public

project.name

4 bit synchronous down counter

4 bit synchronous down counter

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

4 BIT SYNCHRONOUS COUNTER

4 BIT SYNCHRONOUS COUNTER

Public

project.name

4 bit synchronous counter

4 bit synchronous counter

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

SIPO

SIPO

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

4 BIT BIDIRECTIONAL SHIFT REGISTER

4 BIT BIDIRECTIONAL SHIFT REGISTER

Public

project.name

SISO

SISO

Public

project.name

4 bit bidirectional shift register

4 bit bidirectional shift register

Public

project.name

SISO

SISO

Public

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PIPO

PIPO

Public

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SIPO

SIPO

Public

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PIPO

PIPO

Public

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mod 12 counter

mod 12 counter

Public

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mod 7 counter

mod 7 counter

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mod 7 counter

mod 7 counter

Public

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1 TO 16 DEMUX

1 TO 16 DEMUX

Public

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16 TO 1 MUX

16 TO 1 MUX

Public

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DFF USING JKFF

DFF USING JKFF

Public

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TFF USING JKFF

TFF USING JKFF

Public

project.name

JKFF using SRFF

JKFF using SRFF

Public

project.name

16 TO 1 MUX

16 TO 1 MUX

Public

project.name

JK FLIPFLOP

JK FLIPFLOP

Public

project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

Public

project.name

SRFF using DFF

SRFF using DFF

Public

project.name

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

Public

project.name

implementation of full adder with mux and counter

implementation of full adder with mux and counter

Public

project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER

Public

project.name

SRFF USING JKFF

SRFF USING JKFF

Public

project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER

Public

project.name

4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER

Public

project.name

16 TO 1 MUX

16 TO 1 MUX

Public

project.name

PISO

PISO

Public

project.name

TFF USING DFF

TFF USING DFF

Public

project.name

JK FLIPFLOP

JK FLIPFLOP

Public

project.name

SRFF USING TFF

SRFF USING TFF

Public

project.name

4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter

Public

project.name

4 TO 1 MUX

4 TO 1 MUX

Public

project.name

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