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RIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR1 to 16 DEMUX
1 to 16 DEMUX16 to 1 mux
16 to 1 muxSR Flipflop
SR FlipflopTFF USING DFF
TFF USING DFF4 TO 2 ENCODER
4 TO 2 ENCODERDFF USING SRFF
DFF USING SRFFJK FLIPFLOP
JK FLIPFLOPTFF USING SRFF
TFF USING SRFFsynchronous up counter
synchronous up counter24 to 1 MUX using 8 to 1 MUX
24 to 1 MUX using 8 to 1 MUX1 to 4 DEMUX
1 to 4 DEMUX1 to 16 DEMUX
1 to 16 DEMUXVerification of Boolean postulates and laws
Verification of Boolean postulates and lawscounter that counts 0,2,4,7,0
counter that counts 0,2,4,7,0PIPO
PIPOVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsConsensus Theorem
Consensus Theorem8 to 1 MUX
8 to 1 MUXAND USING 2 TO 1 MUX
AND USING 2 TO 1 MUXNAND USING 2 TO 1 MUX
NAND USING 2 TO 1 MUXEXOR USING 2 TO 1 MUX
EXOR USING 2 TO 1 MUXIMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUXPISO
PISOHALF ADDER
HALF ADDER16 to 1 MUX
16 to 1 MUX4 to 1 MUX
4 to 1 MUX2 to 1 MUX
2 to 1 MUXHALF SUBTRACTOR
HALF SUBTRACTOR4 bit bidirectional shift register
4 bit bidirectional shift registerNOR based SR Flipflop
NOR based SR FlipflopNAND GATE
NAND GATERipple carry Adder
Ripple carry AdderNOR GATE
NOR GATEXNOR GATE
XNOR GATERIPPLE CARRY SUBTRACTOR
RIPPLE CARRY SUBTRACTOR4 to 16 decoder
4 to 16 decoderFull adder
Full adderBCD ADDER
BCD ADDERHALF ADDER
HALF ADDERHALF ADDER
HALF ADDERHALF ADDER
HALF ADDERHALF SUBTRACTOR
HALF SUBTRACTORHALF SUBRACTOR
HALF SUBRACTORHALF SUBTRACTOR
HALF SUBTRACTORFULL ADDER
FULL ADDERFULL SUBTRACTOR
FULL SUBTRACTORFULL SUBTRACTOR
FULL SUBTRACTORFULL SUBTRACTOR
FULL SUBTRACTOR4 bit synchronous counter
4 bit synchronous countermod-6 unit distance counter
mod-6 unit distance counterNOT USING 2 TO 1 MUX
NOT USING 2 TO 1 MUXIMPLEMENTATION USING MINTERM USING MUX
IMPLEMENTATION USING MINTERM USING MUXIMPLEMENTATION USING MINTERMS WITH 2:1 MUX
IMPLEMENTATION USING MINTERMS WITH 2:1 MUXSRFF USING JKFF
SRFF USING JKFFSRFF USING TFF
SRFF USING TFFSRFF using DFF
SRFF using DFF1 to 2 decoder
1 to 2 decoder2 BIT MAGNITUDE COMPARATOR
2 BIT MAGNITUDE COMPARATOR4 BIT PARITY GENERATOR
4 BIT PARITY GENERATOR2 TO 4 Decoder
2 TO 4 DecoderFULL ADDER
FULL ADDER3 BIT PARITY CHECKER
3 BIT PARITY CHECKERDecimal to BCD encoder
Decimal to BCD encoderJK FLIPFLOP
JK FLIPFLOPSR FLIPFLOP
SR FLIPFLOPDFF USING JKFF
DFF USING JKFFSIPO
SIPOBinary to Gary code I
Binary to Gary code I3 TO 8 DECODER
3 TO 8 DECODERNAND BASED SR FLIPFLOP
NAND BASED SR FLIPFLOPExcess -3 to BCD I
Excess -3 to BCD I1 to 8 DEMUX
1 to 8 DEMUX4 bit synchronous UP/DOWN counter
4 bit synchronous UP/DOWN counter16 to 1 MUX
16 to 1 MUXFULL ADDER
FULL ADDERVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsBCD to excess -3 converter I
BCD to excess -3 converter I4 bir adder/subtractor
4 bir adder/subtractorSRFF USING JKFF
SRFF USING JKFFT FLIPFLOP
T FLIPFLOP3 BIT PARITY GENERATOR
3 BIT PARITY GENERATOR4 TO 2 Priority encoder
4 TO 2 Priority encoder32 to 1 MUX using 4 to 1 MUX
32 to 1 MUX using 4 to 1 MUXTFF
TFFimplementation of full adder with mux and counter
implementation of full adder with mux and counterSISO
SISOimplementation of full adder using counter
implementation of full adder using counter4 BIT UNIVERSAL SHIFT REGISTER
4 BIT UNIVERSAL SHIFT REGISTEROR GATE
OR GATEI BIT MAGNITUDE COMPARATOR
I BIT MAGNITUDE COMPARATORTFF USING JKFF
TFF USING JKFFFULL SUBTRACTOR
FULL SUBTRACTOR3 BIT PARALLEL MULTIPLIER
3 BIT PARALLEL MULTIPLIERD FLIPFLOP
D FLIPFLOPcircuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0DFF USING TFF
DFF USING TFFVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsimplementation of full adder with mux and counter
implementation of full adder with mux and counterConsensus Theorem
Consensus TheoremFULL ADDER
FULL ADDERVerification of Boolean postulates and laws
Verification of Boolean postulates and lawsXOR GATE
XOR GATEBCD To Decimal decoder
BCD To Decimal decoderIMPLEMENTATION USING MINTERMS WITH MUX
IMPLEMENTATION USING MINTERMS WITH MUXJKFF using SRFF
JKFF using SRFFBCD To 7 segment decoder
BCD To 7 segment decoderD FLIPFLOP
D FLIPFLOP1 to 2 DEMUX
1 to 2 DEMUXNOR USING 2 TO 1 MUX
NOR USING 2 TO 1 MUX3 bit binary counter
3 bit binary countersequence generator using counter
sequence generator using counterbidirectional shift register
bidirectional shift register2 to 1 encoder
2 to 1 encoderNOT GATE
NOT GATEAND GATE
AND GATE4 bit synchronous down counter
4 bit synchronous down counter