project.name

Kiruthiga N

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
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1 to 16 DEMUX

1 to 16 DEMUX
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16 to 1 mux

16 to 1 mux
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SR Flipflop

SR Flipflop
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TFF USING DFF

TFF USING DFF
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4 TO 2 ENCODER

4 TO 2 ENCODER
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DFF USING SRFF

DFF USING SRFF
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JK FLIPFLOP

JK FLIPFLOP
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TFF USING SRFF

TFF USING SRFF
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synchronous up counter

synchronous up counter
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24 to 1 MUX using 8 to 1 MUX

24 to 1 MUX using 8 to 1 MUX
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1 to 4 DEMUX

1 to 4 DEMUX
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1 to 16 DEMUX

1 to 16 DEMUX
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
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PIPO

PIPO
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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project.name
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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project.name
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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Consensus Theorem

Consensus Theorem
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8 to 1 MUX

8 to 1 MUX
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AND USING 2 TO 1 MUX

AND USING 2 TO 1 MUX
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NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
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EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
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IMPLEMENTATION USING MINTERMS WITH MUX

IMPLEMENTATION USING MINTERMS WITH MUX
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PISO

PISO
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HALF ADDER

HALF ADDER
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16 to 1 MUX

16 to 1 MUX
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4 to 1 MUX

4 to 1 MUX
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2 to 1 MUX

2 to 1 MUX
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HALF SUBTRACTOR

HALF SUBTRACTOR
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4 bit bidirectional shift register

4 bit bidirectional shift register
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NOR based SR Flipflop

NOR based SR Flipflop
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NAND GATE

NAND GATE
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Ripple carry Adder

Ripple carry Adder
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NOR GATE

NOR GATE
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XNOR GATE

XNOR GATE
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RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
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4 to 16 decoder

4 to 16 decoder
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Full adder

Full adder
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BCD ADDER

BCD ADDER
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HALF ADDER

HALF ADDER
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HALF ADDER

HALF ADDER
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HALF ADDER

HALF ADDER
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HALF SUBTRACTOR

HALF SUBTRACTOR
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HALF SUBRACTOR

HALF SUBRACTOR
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL ADDER

FULL ADDER
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FULL SUBTRACTOR

FULL SUBTRACTOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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FULL SUBTRACTOR

FULL SUBTRACTOR
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4 bit synchronous counter

4 bit synchronous counter
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mod-6 unit distance counter

mod-6 unit distance counter
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NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
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IMPLEMENTATION USING MINTERM USING MUX

IMPLEMENTATION USING MINTERM USING MUX
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IMPLEMENTATION USING MINTERMS WITH 2:1 MUX

IMPLEMENTATION USING MINTERMS WITH 2:1 MUX
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SRFF USING JKFF

SRFF USING JKFF
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SRFF USING TFF

SRFF USING TFF
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SRFF using DFF

SRFF using DFF
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1 to 2 decoder

1 to 2 decoder
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2 BIT MAGNITUDE COMPARATOR

2 BIT MAGNITUDE COMPARATOR
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4 BIT PARITY GENERATOR

4 BIT PARITY GENERATOR
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2 TO 4 Decoder

2 TO 4 Decoder
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FULL ADDER

FULL ADDER
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3 BIT PARITY CHECKER

3 BIT PARITY CHECKER
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Decimal to BCD encoder

Decimal to BCD encoder
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JK FLIPFLOP

JK FLIPFLOP
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SR FLIPFLOP

SR FLIPFLOP
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DFF USING JKFF

DFF USING JKFF
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SIPO

SIPO
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Binary to Gary code I

Binary to Gary code I
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3 TO 8 DECODER

3 TO 8 DECODER
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NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
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Excess -3 to BCD I

Excess -3 to BCD I
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1 to 8 DEMUX

1 to 8 DEMUX
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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16 to 1 MUX

16 to 1 MUX
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FULL ADDER

FULL ADDER
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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BCD to excess -3 converter I

BCD to excess -3 converter I
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4 bir adder/subtractor

4 bir adder/subtractor
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SRFF USING JKFF

SRFF USING JKFF
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T FLIPFLOP

T FLIPFLOP
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3 BIT PARITY GENERATOR

3 BIT PARITY GENERATOR
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4 TO 2 Priority encoder

4 TO 2 Priority encoder
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32 to 1 MUX using 4 to 1 MUX

32 to 1 MUX using 4 to 1 MUX
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TFF

TFF
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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SISO

SISO
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implementation of full adder using counter

implementation of full adder using counter
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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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OR GATE

OR GATE
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I BIT MAGNITUDE COMPARATOR

I BIT MAGNITUDE COMPARATOR
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TFF USING JKFF

TFF USING JKFF
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FULL SUBTRACTOR

FULL SUBTRACTOR
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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D FLIPFLOP

D FLIPFLOP
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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DFF USING TFF

DFF USING TFF
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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project.name
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Consensus Theorem

Consensus Theorem
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FULL ADDER

FULL ADDER
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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project.name
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XOR GATE

XOR GATE
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BCD To Decimal decoder

BCD To Decimal decoder
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project.name
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IMPLEMENTATION USING MINTERMS WITH MUX

IMPLEMENTATION USING MINTERMS WITH MUX
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project.name
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JKFF using SRFF

JKFF using SRFF
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BCD To 7 segment decoder

BCD To 7 segment decoder
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project.name
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D FLIPFLOP

D FLIPFLOP
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1 to 2 DEMUX

1 to 2 DEMUX
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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3 bit binary counter

3 bit binary counter
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sequence generator using counter

sequence generator using counter
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bidirectional shift register

bidirectional shift register
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2 to 1 encoder

2 to 1 encoder
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NOT GATE

NOT GATE
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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AND GATE

AND GATE
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4 bit synchronous down counter

4 bit synchronous down counter
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Kiruthiga N is not a collaborator of any project.

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