project.name

Bhavadharani.P

Member since: 3 years

Educational Institution: Not Entered

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4 BIT UNIVERSAL SHIFT REGISTER

4 BIT UNIVERSAL SHIFT REGISTER
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4 bit bidirectional shift register

4 bit bidirectional shift register
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4 bit synchronous counter

4 bit synchronous counter
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PISO

PISO
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1 to 8 DEMUX

1 to 8 DEMUX
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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TFF USING SRFF

TFF USING SRFF
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GRAY TO BINARY CODE

GRAY TO BINARY CODE
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4 BIT RIPPLE UP\DOWN COUNTER

4 BIT RIPPLE UP\DOWN COUNTER
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TFF USING JKFF

TFF USING JKFF
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JKFF Using TFF

JKFF Using TFF
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JKFF USING DFF

JKFF USING DFF
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SIPO

SIPO
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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IMPLEMENTATION USING MINTERMS WITH 8:1 MUX

IMPLEMENTATION USING MINTERMS WITH 8:1 MUX
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NAND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX
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4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS

4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS
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3 to 8 DECODER

3 to 8 DECODER
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TFF USING DFF

TFF USING DFF
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D FLIPFLOP

D FLIPFLOP
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SEQUENCE GENERATOR USING COUNTER

SEQUENCE GENERATOR USING COUNTER
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counter that counts 0,2,4,7,0

counter that counts 0,2,4,7,0
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mod-6 unit distance counter

mod-6 unit distance counter
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implementation of full adder using counter

implementation of full adder using counter
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PIPO

PIPO
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PIPO

PIPO
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JK FLIPFLOP

JK FLIPFLOP
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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FULL SUBTRACTOR USING NOR GATES

FULL SUBTRACTOR USING NOR GATES
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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4 to 16 decoder

4 to 16 decoder
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2 x 1 encoder

2 x 1 encoder
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DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
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DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
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8 TO 3 PRIORITY ENCODER

8 TO 3 PRIORITY ENCODER
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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BCD TO DECIMAL DECODER

BCD TO DECIMAL DECODER
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2 TO 4 DECODER

2 TO 4 DECODER
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2 TO 1 MUX

2 TO 1 MUX
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4 to 2 Priority Encoder

4 to 2 Priority Encoder
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AND USING 2 TP 1 MUX

AND USING 2 TP 1 MUX
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4 TO 1 MUX

4 TO 1 MUX
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EXOR USING 2 TO 1 MUX

EXOR USING 2 TO 1 MUX
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8 TO 1 MUX

8 TO 1 MUX
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16 TO 1 MUX

16 TO 1 MUX
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32:1 mux using 4:1 mux

32:1 mux using 4:1 mux
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32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX
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1 TO 2 DEMUX

1 TO 2 DEMUX
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1 TO 4 DEMUX

1 TO 4 DEMUX
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16 TO 1 MUX

16 TO 1 MUX
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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Ripple carry Adder

Ripple carry Adder
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RIPPLE CARRY SUBTRACTOR

RIPPLE CARRY SUBTRACTOR
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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4 BIT ADDER /SUBTRACTOR

4 BIT ADDER /SUBTRACTOR
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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JK FLIPFLOP

JK FLIPFLOP
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DFF USING JKFF

DFF USING JKFF
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T FLIPFLOP

T FLIPFLOP
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BCD to 7 segment decoder

BCD to 7 segment decoder
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OCTAL TO BINARY ENCODER

OCTAL TO BINARY ENCODER
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4 to 2 priority encoder

4 to 2 priority encoder
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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BCD ADDER

BCD ADDER
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SR FLIPFLOP

SR FLIPFLOP
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ASSIGNMENT 2

ASSIGNMENT 2
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1 TO 16 DEMUX

1 TO 16 DEMUX
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4 BIT RIPPLE COUNTER

4 BIT RIPPLE COUNTER
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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4 bit synchronous counter

4 bit synchronous counter
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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JKFF using SRFF

JKFF using SRFF
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1 to 8 DEMUX

1 to 8 DEMUX
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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project.name
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NAND BASED SR FLIPFLOP

NAND BASED SR FLIPFLOP
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BCD to 7 SEGMENT DECODER

BCD to 7 SEGMENT DECODER
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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implementation using minterms with 2:1 MUX

implementation using minterms with 2:1 MUX
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Untitled

Untitled
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TFF

TFF
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IMPLEMENTATION USING MINTERMS WITH 16:1 MUX

IMPLEMENTATION USING MINTERMS WITH 16:1 MUX
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SRFF USING TFF

SRFF USING TFF
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1 to 8 DEMUX

1 to 8 DEMUX
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3 bit binary counter

3 bit binary counter
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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SRFF USING JKFF

SRFF USING JKFF
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NOT USING 2 TO 1 MUX

NOT USING 2 TO 1 MUX
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SISO

SISO
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IMPLEMENTATION USING MINTERNS WITH 4:1 MUX

IMPLEMENTATION USING MINTERNS WITH 4:1 MUX
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DFF USING SRFF

DFF USING SRFF
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4 BIT RIPPLE DOWN COUNTER

4 BIT RIPPLE DOWN COUNTER
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OCTAL TO BINARY ENCODER

OCTAL TO BINARY ENCODER
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SRFF using DFF

SRFF using DFF
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OCTAL TO BINARY ENCODER

OCTAL TO BINARY ENCODER
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24 TO 1 MUX USING 8 TO 1 MUX

24 TO 1 MUX USING 8 TO 1 MUX
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3 BIT PARALLEL MULTIPLIER

3 BIT PARALLEL MULTIPLIER
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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4 bit synchronous counter

4 bit synchronous counter
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MOD 12 COUNTER

MOD 12 COUNTER
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DFF USING TFF

DFF USING TFF
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4 bit synchronous down counter

4 bit synchronous down counter
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OR USING 2 TO 1 MUX

OR USING 2 TO 1 MUX
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4 X 2 ENCODER

4 X 2 ENCODER
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Untitled

Untitled
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32 TO 1 MUX USING 4 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX
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CONSENSUS THEOREM

CONSENSUS THEOREM
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MOD 7 COUNTER

MOD 7 COUNTER
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NOR USING 2 TO 1 MUX

NOR USING 2 TO 1 MUX
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NOR BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP
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