TWO BIT MAGNITUDE COMPARATOR

synchronous up down counter

synchronous up counter

3 BIT PARALLEL MULTIPLIER

4 BIT UP-DOWN COUNTER

AND USING 2 TO 1 MUX

NAND USING 2 TO 1 MUX

BCD TO DECIMAL DECODER

BCD TO EXCESS-3

EXCESS-3 TO BCD

1 BIT MAGNITUDE COMPARATOR

FULL ADDER USING NAND GATES

2 x 1 ENCODER

4 X 2 ENCODER

3 TO 8

SRFF USING JKFF

NAND BASED SR FLIPFLOP

NOR BASED SR FLIPFLOP

SRFF USING JKFF

JKFF USING DFF

SRFF using DFF

SRFF USING TFF

SRFF USING TFF

1:2 DEMUX

1:8 DEMUX

16 to 1 mux

24 to 1 mux using 8 to 1 mux

HALF ADDER USING BASIC GATES

NOR USING 2 TO 1 MUX

JKFF Using TFF

BCD TO 7 SEGMENT DECODER

32 to 1 mux using 4 to 1 mux

FULL ADDER USING BASIC GATES

MUX with counter

counter that counts 0,2,4,7,0

4 TO 16 DECODER

2 to 4 decoder

D FLIPFLOP

1:16 DEMUX

FULL ADDER USING XOR GATE

8 to 1 mux

4-BIT PARITY CHECKER

implementation of full adder with mux and counter

implementation using minterms with 2:1 mux

HALF SUBTRACTOR USING XOR GATE

VERIFICATION OF BOOLEAN LAWS AND POSTULATES

Untitled

JKFF USING DFF

DFF USING JKFF

4 bit synchronous counter

SERIAL IN PARALLEL OUT

parrallel in parallel out

3 bit binary counter

4 TO 2 PRIORITY ENCODER

VERIFICATION OF BOOLEAN ALGEBRA AND POSTULATES

CONSENSUS THEOREM

CONSENSUS THEOREM

8 to 1 mux

16:1 MUX

2 to 1 multiplexer

BINARY TO GRAY CONVERTOR

3- BIT PARITY GENERATOR

2-BIT MAGNITUDE COMPARATOR

Parallel in serial out

VERIFICATION OF BOOLEAN LAWS AND POSTULATES

1:4 DEMUX

Untitled

basic gates

Untitled

FULL ADDER USING NOR GATES

HALF SUBTRACTOR USING NOR GATES

FULL SUBTRACTOR USING NOR GATE

EXOR USING 2 TO 1 MUX

HALF ADDER

HALF ADDER

HALF ADDER USING NOR GATES

OCTAL TO BINARY ENCODER

JK FLIPFLOP

8 TO 3 PRIORITY ENCODER

BCD TO EXCESS-3

DECIMAL TO BCD ENCODER

SERIAL IN SERIAL OUT

DFF USING SRFF

JK FLIPFLOP

SR FLIPFLOP

4:1 mux

HALF SUBTRACTOR USING NAND GATES

VERIFICATION OF BOOLEAN LAWS AND POSTULATES

SRFF using DFF

3- BIT PARITY CHECKER

4 to 1 multiplexer

T FLIPFLOP

4 bit ripple counter with decoded outputs

NAND BASED SR FLIPFLOP

D FLIPFLOP

DFF USING TFF

GRAY TO BINARY CODE

SRFF using DFF

1 TO 2 DECODER

FULL SUBTRACTOR USING NAND GATE

implementation of full adder using counter

4 bit synchronous down counter

JKFF using SRFF

mod-6 unit distance counter

mod-6 unit distance counter

JKFF using SRFF

HALF ADDER USING NAND GATES

HALF SUBTRACTOR USING BASIC GATES

OR USING 2 TO 1 MUX

TFF

4 bit synchronous counter

FULL SUBTRACTOR USING XOR GATE

HALF ADDER USING XOR GATE

bidirectional shift register

SRFF USING TFF

VERIFIVATION OF BOOLEAN LAWS AND POSTULATES

sequence generator using counter

VERIFICATION OF BOOLEAN LAWS AND POSTULATES

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

4 BIT UNIVERSAL SHIFT REGISTER