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K.Redeem Emima

Member since: 4 years

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4 BIT PARITY CHECKER VIII

4 BIT PARITY CHECKER VIII
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Full adder using 2 hald adders

Full adder using 2 hald adders
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AND gate

AND gate
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DE MORGANS THEORM 2

DE MORGANS THEORM 2
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ASSOCIATIVE LAW OF MULTIPLICATION

ASSOCIATIVE LAW OF MULTIPLICATION
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4 bit synchronous counter

4 bit synchronous counter
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DISTRIBUTIVE PROPERTY 2

DISTRIBUTIVE PROPERTY 2
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2 TO 1 MUX

2 TO 1 MUX
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8 TO 1 MUX

8 TO 1 MUX
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4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS

4-BIT RIPPLE COUNTER WITH DECODED OUTPUTS
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4 BIT RIPPLE COUNTER

4 BIT RIPPLE COUNTER
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MOD 12 COUNTER

MOD 12 COUNTER
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4 bit synchronous UP/DOWN counter

4 bit synchronous UP/DOWN counter
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FULL ADDER-NAND NAND IMPLEMENTATION

FULL ADDER-NAND NAND IMPLEMENTATION
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Verification of Boolean postulates and laws

Verification of Boolean postulates and laws
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implementation of full adder with mux and counter

implementation of full adder with mux and counter
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Half adder using minimal number of NAND gates

Half adder using minimal number of NAND gates
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Demorgans theorem-I

Demorgans theorem-I
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4 bit synchronous down counter

4 bit synchronous down counter
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MOD 12 COUNTER

MOD 12 COUNTER
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FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
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MOD 7 COUNTER

MOD 7 COUNTER
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NOR gate

NOR gate
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COMMUTATIVE LAW OF ADDITION

COMMUTATIVE LAW OF ADDITION
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NOT

NOT
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Demorgans theprem-II

Demorgans theprem-II
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DISTRIBUTIVE PROPERTY

DISTRIBUTIVE PROPERTY
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Half subtractor using basic gates

Half subtractor using basic gates
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Hlaf adder

Hlaf adder
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OR

OR
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EX-OR gate

EX-OR gate
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NAND gate

NAND gate
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EX NOR

EX NOR
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ABSORPTION LAW 2

ABSORPTION LAW 2
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CONSENSUS THEROEM

CONSENSUS THEROEM
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Half adder using basic gates

Half adder using basic gates
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FULL ADDER USING BASIC GATES

FULL ADDER USING BASIC GATES
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4 bit ripple counter

4 bit ripple counter
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4 bit ripple down counter

4 bit ripple down counter
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ABSORPTION LAW 1

ABSORPTION LAW 1
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16 TO 1 MUX

16 TO 1 MUX
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Untitled

Untitled
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FULL ADDER USING BASIC GATE

FULL ADDER USING BASIC GATE
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CONSENSUS LAW

CONSENSUS LAW
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AND gate

AND gate
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VERIFICAT

VERIFICAT
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Untitled

Untitled
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DECIMAL TO BCD ENCODER

DECIMAL TO BCD ENCODER
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HALF SUBTRACTOR

HALF SUBTRACTOR
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FULL ADDER USING BASIC GATE

FULL ADDER USING BASIC GATE
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2- BIT MAGNITUDE COMPARATOR

2- BIT MAGNITUDE COMPARATOR
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implementation of full adder using counter

implementation of full adder using counter
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circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0
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4 bit ripple counter with decoded outputs

4 bit ripple counter with decoded outputs
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COMMUTATIVE LAW OF MULTIPLICATION

COMMUTATIVE LAW OF MULTIPLICATION
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ASSOCIATIVE LAW OF ADDITION

ASSOCIATIVE LAW OF ADDITION
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FULL ADDER USING NOR GATES

FULL ADDER USING NOR GATES
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VERFICATION OF BOOLEAN LAWS AND POSTULATES

VERFICATION OF BOOLEAN LAWS AND POSTULATES
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