V.GURUARCHANA
Member since: 4 years
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3.CODE CONVERTER
3.CODE CONVERTER
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
ASYNCHRONOUS MOD 12 COUNTER
ASYNCHRONOUS MOD 12 COUNTER
3.CODE CONVERTER
3.CODE CONVERTER
3.CODE CONVERTER
3.CODE CONVERTER
4 BIT RIPPLE DOWN COUNTER
4 BIT RIPPLE DOWN COUNTER
CODE CONVERTER
CODE CONVERTER
SYNCHRONOUS EVEN DOWN COUNTER
SYNCHRONOUS EVEN DOWN COUNTER
FULL ADDER USING MUX WITH COUNTER
FULL ADDER USING MUX WITH COUNTER
Untitled
Untitled
3.CODE CONVERTER
3.CODE CONVERTER
full adder with counter
full adder with counter
3.CODE CONVERTER
3.CODE CONVERTER
4 BIT SYNCHRONOUS COUNTER
4 BIT SYNCHRONOUS COUNTER
VERIFICATION OF CONSENSUS LAWB
VERIFICATION OF CONSENSUS LAWB
CODE CONVERTER
CODE CONVERTER
VERIFICATION OF CONSENSUS LAW BY USING TRUTH TABLE
VERIFICATION OF CONSENSUS LAW BY USING TRUTH TABLE
3.CODE CONVERTER
3.CODE CONVERTER
3.CODE CONVERTER
3.CODE CONVERTER
ASYNCHRONOUS MOD 7 COUNTER
ASYNCHRONOUS MOD 7 COUNTER
SYNCHRONOUS ODD UP COUNTER
SYNCHRONOUS ODD UP COUNTER
3.CODE CONVERTER
3.CODE CONVERTER
4 BIT SYNCHRONOUS DOWN COUNTER
4 BIT SYNCHRONOUS DOWN COUNTER
8 TO 3 PRIORITY ENCODER
8 TO 3 PRIORITY ENCODER
4 BIT RIPPLE UP/DOWN COUNTER
4 BIT RIPPLE UP/DOWN COUNTER
2. VERIFICATION OF BOOLEAN POSTULATES AND LAWS
2. VERIFICATION OF BOOLEAN POSTULATES AND LAWS
4 BIT SYNCHRONOUS UP/DOWN COUNTER
4 BIT SYNCHRONOUS UP/DOWN COUNTER
2.VERIFICATION OF BOOLEAN POSTULATES AND LAWS
2.VERIFICATION OF BOOLEAN POSTULATES AND LAWS
32:1 mux using 4:1 mux
32:1 mux using 4:1 mux
4 BIT RIPPLE COUNTER WITH DECODER OUTPUTS
4 BIT RIPPLE COUNTER WITH DECODER OUTPUTS
3.CODE CONVERTER
3.CODE CONVERTER
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