JKFF USING DFF

4 BIT PARITY GENERATOR AND CHECKER

HALF ADDER USING BASIC GATE

4 bit synchronous UP/DOWN counter

ASSOCIATIVE PROPERTY OF MULTIPLICATION

4*2 ENCODER

BINARY TO GRAY CODE CONVERTER

1-BIT MAGNITUDE COMPARATOR

FullAdder From 2 HalfAdders

MUX with counter

3 bit binary counter

24 TO1 MUX USIN

1

1

1

1

4 to 1 MUX

8 TO 1

1

Untitled

3 BIT PARITY GENERATOR AND CHECKER

Untitled

Untitled

NOT 2 TO 1 MUX

NAND USING 2 TO 1 MUX

EXOR 2 TO 1 MUX

32 TO 1 MUX USING 4 TO 1 MUX

1:2 DEMUX

FULL ADDER USING BASIC GATES

DISTRIBUTIVE PROPERTY

gate

1:8 DEMUX

ASSOCIATIVE PROPERTY

CONSENUS THEOREM

IMPLEMENTATION USING MINTERM WITH 2: 1 MUX

SRFF USING DFF

gates for BCD to 7 segment decoder

counter that counts 0,2,4,7,0

Untitled

8 to 3 priority encoder

circuit that counts (0,2,4...14)when input is 1 and counts (1,3...15)when input is 0

FULL SUBTRACTOR USING BASIC GATES

commutative property

ASSOCIATIVE PROPERTY

ASSOCIATIVE PROPERTY

ASSOCIATIVE PROPERTY

ASSOCIATIVE PROPERTY

ABSORPTION LAW 2

2 TO 4 DECODER

1 TO 2 DECODER

DISTRIBUTIVE PROPERTY

DISTRIBUTIVE PROPERTY OF MULTIPLCATION

DISTRIBUTIVE PROPERTY

DISTRIBUTIVE PROPERTY

CONSENUS THEOREM

CONSENUS THEOREM

CONSENUS THEOREM

CONSENUS THEOREM

BCD TO DECIMAL DECODER

Untitled

FULL SUBTRACTOR USING NAND GATE

4 to 16 decoder

4 to 16 decoder

BCD TO 7 SEGMENT DECODER

2 * 1 ENCODER

HALF SUBTRATOR USING XOR GATE

OCTAL TO BINARY

FULL ADDER USING NOR GATE

FULL ADDER USING XOR

Untitled

HALF ADDER USING NAD GATE

HALF SUBTRATOR USING NAND GATE

HALF SUBTRATOR USING NOR GATES

FULL SUBTRACTOR USING XOR GATES

Decimal TO BCD Encoder

4 to 2 priority encoder

16 TO 1 MUX

4 BIT PARITY GENERATOR AND CHECKER

GRAY TO BINARY CONVERTER

4 bit bidirectional shift register

4 BIT RIPPLE COUNTER

mod-6 unit distance counter

AND 2 TO 1 MUX

BCD TO 7 SEGEMENT DECODER

gates for BCD to 7 segment decoder

SISO

ABSORPTION LAW 3

JKFF USING TFF

DFF USING TFF

TFF USING DFF

1:4 DEMUX

ASSOCIATIVE PROPERTY

COMMUTATIVE PROPERTY

CONSENUS THEOREM

ASSOCIATIVE PROPERTY

3 to 8

ABSORPTION LAW 4

consenus theorem

HALF SUBRACTOR USING BASIC GATES

4-Bit Full Adder

4 BIT RIPPLE COUNTER WITH DECODED OUTUTS

MOD 12 COUNTER

NAND BASED SR FLIPFLOP

SR FLIPFLOP

T FLIPFLOP

DFF USING JKFF

TFF USING SRFF

TFF USING JKFF

SRFF USING TFF

4-BIT RIPPLE DOWN COUNTER

BCD TO EXCESS 3 CONVERTER

3 BIT PARITY GENERATOR AND CHECKER

8 TO 3 PRIORITY ENCODER

Full subtractor from Half subtractor

Ripple carry subtractor

3 BIT PARALLEL MULTIPLER

D FLIPFLOP

D FLIPFLOP

T FLIPFLOP

SRFF USING JKFF

4 BIT RIPPLE COUNTER WITH DECODER OUTPUTS

MOD 7 COUNTER

NOR BASED SR FLIPFLOP

ABSORPTION LAW 1

DFF USING SRFF

HALF ADDER USING XOR GATE

HALF ADDER USING NOR GATE

PIPO

DISTRIBUTIVE PROPERTY OF ADDITION

JK FLIPFLOP

IMPLEMENTATION OF MINTERM USING 8:1 MUX

4 BIT RIPPLE UP/DOWN COUNTER

24 TO I MUX USING 8 TO 1 MUX

4 BIT PARALLEL ADDER/SUBTRACTOR

SIPO

CONSENUS THEOREM

4 bit synchronous down counter

4 BIT UNIVERSAL SHIFT REGISTER

PISO

2 TO 1 MUX

sequence generator using counter

4-bit full adder circuit

JK FLIPFLOP

JKFF USING SRFF

2-BIT MAGNITUDE COMPARATOR

DISTRIBUTIVE PROPERTY

OR 2 TO 1 MUX

DISTRIBUTIVE PROPERTY

IMPLEMENTION USING MINTERM WITH 4:1 MUX

IMPLEMENTATION USING MINTERMS WITH 16:1 MUX

NOR 2 TO 1 MUX

FULL ADDER USING XOR GATE