Member since: 4 years
Educational Institution: MEPCO SCHLENK ENGINNERING COLLEGE,SIVAKASI
Country: India
CODE CONVERTERS
CODE CONVERTERSMUX AND DEMUX
MUX AND DEMUXUntitled
UntitledFULL SUBTRACTOR USING NAND GATES
FULL SUBTRACTOR USING NAND GATESf6tyutyutyyruru
f6tyutyutyyruruHALF SUBTRACTOR using XOR gate
HALF SUBTRACTOR using XOR gaterealisation of J-FF using D-FF
realisation of J-FF using D-FFrealisation of D-FF using JK-FF
realisation of D-FF using JK-FFFULLSUBTRATOR using basic gates
FULLSUBTRATOR using basic gatesF(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)32 TO 1 USING 4 TO 1 MUX
32 TO 1 USING 4 TO 1 MUXrealisation of T-FF using SR-FF
realisation of T-FF using SR-FFAND GATE
AND GATEAND GATE
AND GATEMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKERAND
ANDUntitled
UntitledHALF ADDER using XOR gates
HALF ADDER using XOR gatesHALF SUBTRATOR using NOR gates
HALF SUBTRATOR using NOR gatesF(A,B,C,D)=Em(6,8,9,10,11,12,14)
F(A,B,C,D)=Em(6,8,9,10,11,12,14)MUX AND DEMUX
MUX AND DEMUXMUX AND DEMUX
MUX AND DEMUXNAND based SR-FF
NAND based SR-FF4 BIT EXESS TO BCD
4 BIT EXESS TO BCD4 BIT RIPPLE CARRY ADDER
4 BIT RIPPLE CARRY ADDERD-FF using NAND gate
D-FF using NAND gateF(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)Toggle Flip Flop usinG NAND gate
Toggle Flip Flop usinG NAND gaterealisation ofJ-FF using SR-FF
realisation ofJ-FF using SR-FFrealisation of D-FF using SR-FF
realisation of D-FF using SR-FFMUX AND DEMUX
MUX AND DEMUXHALF SUBTRATOR using NAND gates only
HALF SUBTRATOR using NAND gates onlyMUX AND DEMUX
MUX AND DEMUXMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKERD-FF using NAND gate
D-FF using NAND gaterealisation of SR-FF using D-FF
realisation of SR-FF using D-FFMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKER8 TO 1 DEMUX
8 TO 1 DEMUXJK-FF using NAND gate
JK-FF using NAND gate4 BIT ADDER/SUBTRACTOR
4 BIT ADDER/SUBTRACTORMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKER4 BIT RIPPLE CAFRY SUBTRACTOR
4 BIT RIPPLE CAFRY SUBTRACTORMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKERHALF ADDER using NOR gates
HALF ADDER using NOR gatesBCD AADER
BCD AADERFULLSUBTRATROR using XOR gates
FULLSUBTRATROR using XOR gatesNOR -based SR-FF
NOR -based SR-FF4 BIT BCD TO EXCESS 3
4 BIT BCD TO EXCESS 3realisation of T-FF using D-FF
realisation of T-FF using D-FFMUX AND DEMUX
MUX AND DEMUXMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKERrealisation of D-FF using SR-FF
realisation of D-FF using SR-FFF(A,B,C,D)=Em(6,8,9,10,11,12,14)
F(A,B,C,D)=Em(6,8,9,10,11,12,14)4 BIT BINARY TO GRAY
4 BIT BINARY TO GRAYFULL SUBTRACTOR USING NAND GATES
FULL SUBTRACTOR USING NAND GATESMUX AND DEMUX
MUX AND DEMUXF(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)F(A,B,C,D)=Em(6,8,9,10,11,12,14)
F(A,B,C,D)=Em(6,8,9,10,11,12,14)full adder using basic gates
full adder using basic gatesHALF ADDER using NAND logic
HALF ADDER using NAND logicMASTER SLAVE -FF using NAND gate
MASTER SLAVE -FF using NAND gateMUX AND DEMUX
MUX AND DEMUXMAGNITUDE COMPARATOR AND PARITY CHECKER
MAGNITUDE COMPARATOR AND PARITY CHECKERFULLADDER using XOR
FULLADDER using XORF(A,B,C,D)=Em(6,8,9,10,11,12,14)
F(A,B,C,D)=Em(6,8,9,10,11,12,14)Full adder using NAND gates
Full adder using NAND gates