project.name

sarveshwaran.S

Member since: 4 years

Educational Institution: MEPCO SCHLENK ENGINNERING COLLEGE,SIVAKASI

Country: India

CODE CONVERTERS

CODE CONVERTERS
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

Untitled

Untitled
Public
project.name

FULL SUBTRACTOR USING NAND GATES

FULL SUBTRACTOR USING NAND GATES
Public
project.name

f6tyutyutyyruru

f6tyutyutyyruru
Public
project.name

HALF SUBTRACTOR using XOR gate

HALF SUBTRACTOR using XOR gate
Public
project.name

realisation of J-FF using D-FF

realisation of J-FF using D-FF
Public
project.name

realisation of D-FF using JK-FF

realisation of D-FF using JK-FF
Public
project.name

FULLSUBTRATOR using basic gates

FULLSUBTRATOR using basic gates
Public
project.name

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
Public
project.name

32 TO 1 USING 4 TO 1 MUX

32 TO 1 USING 4 TO 1 MUX
Public
project.name

realisation of T-FF using SR-FF

realisation of T-FF using SR-FF
Public
project.name

AND GATE

AND GATE
Public
project.name

AND GATE

AND GATE
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

AND

AND
Public
project.name

Untitled

Untitled
Public
project.name

HALF ADDER using XOR gates

HALF ADDER using XOR gates
Public
project.name

HALF SUBTRATOR using NOR gates

HALF SUBTRATOR using NOR gates
Public
project.name

F(A,B,C,D)=Em(6,8,9,10,11,12,14)

F(A,B,C,D)=Em(6,8,9,10,11,12,14)
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

NAND based SR-FF

NAND based SR-FF
Public
project.name

4 BIT EXESS TO BCD

4 BIT EXESS TO BCD
Public
project.name

4 BIT RIPPLE CARRY ADDER

4 BIT RIPPLE CARRY ADDER
Public
project.name

D-FF using NAND gate

D-FF using NAND gate
Public
project.name

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
Public
project.name

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
Public
project.name

Toggle Flip Flop usinG NAND gate

Toggle Flip Flop usinG NAND gate
Public
project.name

realisation ofJ-FF using SR-FF

realisation ofJ-FF using SR-FF
Public
project.name

realisation of D-FF using SR-FF

realisation of D-FF using SR-FF
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

HALF SUBTRATOR using NAND gates only

HALF SUBTRATOR using NAND gates only
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

D-FF using NAND gate

D-FF using NAND gate
Public
project.name

realisation of SR-FF using D-FF

realisation of SR-FF using D-FF
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

8 TO 1 DEMUX

8 TO 1 DEMUX
Public
project.name

JK-FF using NAND gate

JK-FF using NAND gate
Public
project.name

4 BIT ADDER/SUBTRACTOR

4 BIT ADDER/SUBTRACTOR
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

4 BIT RIPPLE CAFRY SUBTRACTOR

4 BIT RIPPLE CAFRY SUBTRACTOR
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

HALF ADDER using NOR gates

HALF ADDER using NOR gates
Public
project.name

BCD AADER

BCD AADER
Public
project.name

FULLSUBTRATROR using XOR gates

FULLSUBTRATROR using XOR gates
Public
project.name

NOR -based SR-FF

NOR -based SR-FF
Public
project.name

4 BIT BCD TO EXCESS 3

4 BIT BCD TO EXCESS 3
Public
project.name

realisation of T-FF using D-FF

realisation of T-FF using D-FF
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

realisation of D-FF using SR-FF

realisation of D-FF using SR-FF
Public
project.name

F(A,B,C,D)=Em(6,8,9,10,11,12,14)

F(A,B,C,D)=Em(6,8,9,10,11,12,14)
Public
project.name

4 BIT BINARY TO GRAY

4 BIT BINARY TO GRAY
Public
project.name

FULL SUBTRACTOR USING NAND GATES

FULL SUBTRACTOR USING NAND GATES
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)

F(A,B,C,D)=Em(1,3,5,6,8,10,11,12,14)
Public
project.name

F(A,B,C,D)=Em(6,8,9,10,11,12,14)

F(A,B,C,D)=Em(6,8,9,10,11,12,14)
Public
project.name

full adder using basic gates

full adder using basic gates
Public
project.name

HALF ADDER using NAND logic

HALF ADDER using NAND logic
Public
project.name

MASTER SLAVE -FF using NAND gate

MASTER SLAVE -FF using NAND gate
Public
project.name

MUX AND DEMUX

MUX AND DEMUX
Public
project.name

MAGNITUDE COMPARATOR AND PARITY CHECKER

MAGNITUDE COMPARATOR AND PARITY CHECKER
Public
project.name

FULLADDER using XOR

FULLADDER using XOR
Public
project.name

F(A,B,C,D)=Em(6,8,9,10,11,12,14)

F(A,B,C,D)=Em(6,8,9,10,11,12,14)
Public
project.name

Full adder using NAND gates

Full adder using NAND gates
Public
project.name
No result image
sarveshwaran.S doesn't have any favourites.
No result image
sarveshwaran.S is not a collaborator of any project.