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experiment 10
experiment 10experiment 12
experiment 12experiment 2
experiment 2Binary to Grey
Binary to Greyexperiment 7(b)
experiment 7(b)binary to gray
binary to grayexperiment 12
experiment 122
2Greay to Binary
Greay to Binaryproject 15
project 15Harshit
HarshitHarshit
HarshitEXP 14A
EXP 14AExp 13-Part b
Exp 13-Part bT---Flip flop
T---Flip flopD Lactch using NOR
D Lactch using NORExperiment-8
Experiment-8Untitled
Untitled17 A
17 A3-8
3-8exp4
exp4Exp - 9 (A)
Exp - 9 (A)project 2
project 2Untitled
Untitledhalf adder
half adderClocked SR latches
Clocked SR latchesSR Flip-flops
SR Flip-flopsSR LATCH
SR LATCHlog2
log2Multiplexer 8x1
Multiplexer 8x1exp15 alu
exp15 aluSR LATCH
SR LATCHflip-flop
flip-flop2 to 4 decode circuit
2 to 4 decode circuitexperiment-7
experiment-7T---Flip Flop
T---Flip FlopT---Flip flop
T---Flip flopExperiment 8
Experiment 8Untitled
UntitledUntitled
UntitledExp - 9(B)
Exp - 9(B)lab3_updated
lab3_updatedGrey to Binary
Grey to BinaryAssignment
AssignmentJK and Tflip flop
JK and Tflip flopshift left
shift leftExp - 9 (A)
Exp - 9 (A)Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1sJK FLIP FLOP USING D
JK FLIP FLOP USING DExperiment 12
Experiment 12Master Slave
Master SlaveLAB_1 LOGIC GATES
LAB_1 LOGIC GATESEXP-12
EXP-12project 11
project 11JK FLIP FLOP USING D
JK FLIP FLOP USING DHarshit
Harshit