Harshit Gupta
Member since: 4 years
Educational Institution: Not Entered
Country: Not Entered
experiment 12
experiment 12
experiment 2
experiment 2
experiment 7(b)
experiment 7(b)
experiment 12
experiment 12
T---Flip flop
T---Flip flop
2 to 4 decode circuit
2 to 4 decode circuit
2
2
Greay to Binary
Greay to Binary
project 15
project 15
Harshit
Harshit
Harshit
Harshit
exp4
exp4
Experiment-8
Experiment-8
3-8
3-8
Exp - 9 (A)
Exp - 9 (A)
project 2
project 2
Untitled
Untitled
Clocked SR latches
Clocked SR latches
SR Flip-flops
SR Flip-flops
SR LATCH
SR LATCH
exp15 alu
exp15 alu
SR LATCH
SR LATCH
17 A
17 A
binary to gray
binary to gray
T---Flip Flop
T---Flip Flop
T---Flip flop
T---Flip flop
Experiment 8
Experiment 8
Untitled
Untitled
Untitled
Untitled
Exp - 9(B)
Exp - 9(B)
lab3_updated
lab3_updated
Grey to Binary
Grey to Binary
flip-flop
flip-flop
Assignment
Assignment
JK and Tflip flop
JK and Tflip flop
shift left
shift left
Exp - 9 (A)
Exp - 9 (A)
JK FLIP FLOP USING D
JK FLIP FLOP USING D
Experiment 12
Experiment 12
Exp 13-Part b
Exp 13-Part b
Binary to Grey
Binary to Grey
EXP 14A
EXP 14A
EXP-12
EXP-12
experiment 10
experiment 10
experiment-7
experiment-7
project 11
project 11
D Lactch using NOR
D Lactch using NOR
JK FLIP FLOP USING D
JK FLIP FLOP USING D
Multiplexer 8x1
Multiplexer 8x1
half adder
half adder
log2
log2
Untitled
Untitled
Master Slave
Master Slave
LAB_1 LOGIC GATES
LAB_1 LOGIC GATES
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Harshit
Harshit
