project.name

Akhilesh Verma

Member since: 843 days

Educational Institution: Ajay Kumar Garg Engineering College

Country: India

test

test
Public
test

SISO

SISO
Public
SISO

alu

alu
Public
alu

Untitled

Untitled
Public
Untitled

N bit adder

N bit adder
Public
N bit adder

cu

cu
Public
cu

counter

counter
Public
counter

counter

counter
Public
counter

Data Path using MUX and decoder

Data Path using MUX and decoder
Public
Data Path using MUX and decoder

4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
Public
4 Bit Carry Look ahead adder

Lab-2

Lab-2
Public
Lab-2

hi

hi
Public
hi

cl

cl
Public
cl

vb

vb
Public
vb

Untitled

Untitled
Public
Untitled

Untitled

Untitled
Public
Untitled

multi wire

multi wire
Public
multi wire

1 bit alu 8 bit alu

1 bit alu 8 bit alu
Public
1 bit alu 8 bit alu

Lab-1

Lab-1
Public
Lab-1

one bit ALU

one bit ALU
Public
one bit ALU

1-bit ALU

1-bit ALU
Public
1-bit ALU

4 bit adder sub

4 bit adder sub
Public
4 bit adder sub

Data Path using MUX and decoder

Data Path using MUX and decoder
Public
Data Path using MUX and decoder

8 Bit Asy Counter with Hex Display

8 Bit Asy Counter with Hex Display
Public
8 Bit Asy Counter with Hex Display

Radix-4 Booth Multiplier

Radix-4 Booth Multiplier
Public
Radix-4 Booth Multiplier

Registers

Registers
Public
Registers

counter

counter
Public
counter

Datapath

Datapath
Public
Datapath

Activity 3.4

Activity 3.4
Public
Activity 3.4

Experiment 5 (8 Bit Input Output System)

Experiment 5 (8 Bit Input Output System)
Public
 Experiment 5 (8 Bit Input Output System)

Femto-4v2.6 (Computer)

Femto-4v2.6 (Computer)
Public
Femto-4v2.6 (Computer)

Multiplier

Multiplier
Public
Multiplier

Activity 3.4

Activity 3.4
Public
Activity 3.4

4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
Public
4 Bit Carry Look ahead adder