project.name

Akhilesh Verma

Member since: 4 years

Educational Institution: Ajay Kumar Garg Engineering College

Country: India

SISO

SISO
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alu

alu
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Untitled

Untitled
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cu

cu
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Untitled

Untitled
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4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
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project.name
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hi

hi
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Data Path using MUX and decoder

Data Path using MUX and decoder
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project.name
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Data Path using MUX and decoder

Data Path using MUX and decoder
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4 bit adder sub

4 bit adder sub
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N bit adder

N bit adder
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Ring Counter

Ring Counter
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yyu

yyu
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cl

cl
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vb

vb
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Untitled

Untitled
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multi wire

multi wire
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1 bit alu 8 bit alu

1 bit alu 8 bit alu
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project.name
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one bit ALU

one bit ALU
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1-bit ALU

1-bit ALU
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Ripple Carry Adder

Ripple Carry Adder
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jonshon counter

jonshon counter
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Data Path using MUX and decoder

Data Path using MUX and decoder
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Datapath

Datapath
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Activity 3.4

Activity 3.4
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Experiment 5 (8 Bit Input Output System)

Experiment 5 (8 Bit Input Output System)
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test

test
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counter

counter
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Untitled

Untitled
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Lab-1

Lab-1
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Femto-4v2.6 (Computer)

Femto-4v2.6 (Computer)
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project.name
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counter

counter
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counter

counter
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Radix-4 Booth Multiplier

Radix-4 Booth Multiplier
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project.name
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8 Bit Asy Counter with Hex Display

8 Bit Asy Counter with Hex Display
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project.name
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8 Bit Asy Counter with Hex Display

8 Bit Asy Counter with Hex Display
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Lab-2

Lab-2
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Multiplexers using logic gates

Multiplexers using logic gates
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Multiplexers using logic gates

Multiplexers using logic gates
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Multiplier

Multiplier
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Registers

Registers
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Activity 3.4

Activity 3.4
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4 Bit Carry Look ahead adder

4 Bit Carry Look ahead adder
Public
project.name
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