Member since: 4 years
Educational Institution: k.I.E.T
Country: India
aakash5b
aakash5bmaster slave using d flip flop
master slave using d flip flopUntitled
Untitledhalf adder full adder half subtractor full subtractor
half adder full adder half subtractor full subtractornand sr latch usins clock
nand sr latch usins clockD LATCH USING NOR
D LATCH USING NORdemultiplexer 0f 1x8
demultiplexer 0f 1x8Untitled
Untitledexp3
exp3exp 10 demultiplexer
exp 10 demultiplexerexp3
exp3MULTIPLEXER 4X1
MULTIPLEXER 4X1design of clocked sequential circuit
design of clocked sequential circuitjk flip flop
jk flip flopSR CIRCUIT(RACE CONDITION)
SR CIRCUIT(RACE CONDITION)JK USING D FLIP FLOP
JK USING D FLIP FLOPdesign of clocked sequential circuit
design of clocked sequential circuitDecoder of 2x4
Decoder of 2x4experiment3
experiment3LOGIC UNIT
LOGIC UNITENCODER OF 4X2
ENCODER OF 4X2Untitled
Untitledaakash mittal2
aakash mittal2aakash mittal
aakash mittal3X3 ARRAY MULTIPLIER
3X3 ARRAY MULTIPLIERaakash4.c
aakash4.cUntitled
UntitledDecoder of 2x4
Decoder of 2x4DECODER OF 3X8
DECODER OF 3X8nand latch
nand latchproject2
project2aaksh mittal
aaksh mittalEXPERIMENT6B
EXPERIMENT6Baakash5
aakash5MULTIPLEXER OF 8X3
MULTIPLEXER OF 8X3sequential circuit using d flip flop
sequential circuit using d flip flopENCODER OF 8X3
ENCODER OF 8X3t flip-flop
t flip-flopimlement of full adder full subtractor half adder half subtractor
imlement of full adder full subtractor half adder half subtractoraakash mittal
aakash mittalCONTROLLED SR LATCH USING NOR
CONTROLLED SR LATCH USING NORsr latch
sr latchD LATCH USING NAND
D LATCH USING NANDSEQUENTIAL CIRCUIT USING JK FLIP FLOP
SEQUENTIAL CIRCUIT USING JK FLIP FLOP4 BIT ARITHMETIC AND LOGIC UNIT
4 BIT ARITHMETIC AND LOGIC UNIT