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Aditya Khare

Member since: 3 years

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BTOG ADITYA

BTOG ADITYA
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Master Slave

Master Slave
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1*8 demultiplexer

1*8 demultiplexer
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Exp7.1

Exp7.1
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Clocked SR using NAND

Clocked SR using NAND
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2*2mul

2*2mul
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D latch using NOR

D latch using NOR
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Modified SR circuit

Modified SR circuit
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Experiment 15A

Experiment 15A
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Experiment 14B

Experiment 14B
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Universal Register Exp 17

Universal Register Exp 17
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1*8 demultiplexer

1*8 demultiplexer
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experiment 17 JK right shift

experiment 17 JK right shift
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SR Latch

SR Latch
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State Diagram or table

State Diagram or table
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Experiment 9A

Experiment 9A
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Experiment 15B

Experiment 15B
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3 to 8 line decoder

3 to 8 line decoder
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EXP 17 shift left using D

EXP 17 shift left using D
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Exp 17 shift right using D

Exp 17 shift right using D
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2 to 4 line decoder

2 to 4 line decoder
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Untitled

Untitled
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Untitled

Untitled
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2*4 decoder

2*4 decoder
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3*8 decoder

3*8 decoder
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Exp 8a

Exp 8a
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3 bit circuit

3 bit circuit
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Exp 11 A

Exp 11 A
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Clocked SR using NOR

Clocked SR using NOR
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Untitled

Untitled
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Experiment 8b

Experiment 8b
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GTOB ADITYA

GTOB ADITYA
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3*3Mul

3*3Mul
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Experiment 9B

Experiment 9B
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7A exp

7A exp
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Full Adder From 2 half Adders

Full Adder From 2 half Adders
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experiment 17 shift left jk

experiment 17 shift left jk
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T FLIP FLOP

T FLIP FLOP
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J K flip flop using D

J K flip flop using D
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1*4 demultiplexer

1*4 demultiplexer
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Experiment 16

Experiment 16
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D latch using NAND

D latch using NAND
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Full Adder From 2 half Adders

Full Adder From 2 half Adders
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