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Shafali Sharma

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

ALU

ALU
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SISO and SIPO

SISO and SIPO
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d flip flops

d flip flops
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3 by 8 decoder corrected

3 by 8 decoder corrected
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3 by 8 decoder

3 by 8 decoder
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SR flip flop

SR flip flop
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demux 4*1

demux 4*1
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exp 10 (b)

exp 10 (b)
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exp 10 (a)

exp 10 (a)
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jk flip flop

jk flip flop
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Arithmetic logic unit

Arithmetic logic unit
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SISO and SIPO

SISO and SIPO
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1X4 DEMULTIPLEXER

1X4 DEMULTIPLEXER
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PIPO

PIPO
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Carry LOok ahead

Carry LOok ahead
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binary to gray and vice versa

binary to gray and vice versa
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JK flip flop

JK flip flop
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exp 6(b)

exp 6(b)
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3 bit binary adder and subtractor

3 bit binary adder and subtractor
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Carry Look Ahead

Carry Look Ahead
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ALU

ALU
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Priority Encoder

Priority Encoder
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3X8 DEMULTIPLEXER

3X8 DEMULTIPLEXER
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ALU Circuit design

ALU Circuit design
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2 Bit ALU

2 Bit ALU
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Exp. 6-> 2*2 Binary Multiplier

Exp. 6-> 2*2 Binary Multiplier
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2*2 Binary Multiplier

2*2 Binary Multiplier
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2 to 4 decoder

2 to 4 decoder
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adders and subtractors-half & full

adders and subtractors-half & full
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exp 11A

exp 11A
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Untitled

Untitled
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PISO

PISO
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SISO and SIPO

SISO and SIPO
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gates

gates
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Untitled

Untitled
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SISO and SIPO

SISO and SIPO
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DEMUL

DEMUL
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EXPERIMENT 9 4X1MUX

EXPERIMENT 9 4X1MUX
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Untitled

Untitled
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3-bit parallel binary Adder/Subbtractor

3-bit parallel binary Adder/Subbtractor
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Shafali Sharma is not a collaborator of any project.

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