project.name

Utkarsh Saxena

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

PISO

PISO
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8X1 Multiplexer Assesment

8X1 Multiplexer Assesment
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Priority Encoder

Priority Encoder
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4X1 MUX

4X1 MUX
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8X1 MUX

8X1 MUX
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XNOR Gate

XNOR Gate
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Arithmetic logic unit

Arithmetic logic unit
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4X1 Multiplexer

4X1 Multiplexer
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N -Parallel Subtractor

N -Parallel Subtractor
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NOR Gate

NOR Gate
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NAND Gate

NAND Gate
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XOR Gate

XOR Gate
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3 - Bit Parallel Adder

3 - Bit Parallel Adder
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Binary To Gray Code

Binary To Gray Code
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PIPO

PIPO
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Priority Encoder

Priority Encoder
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1X8 De-Multiplexer

1X8 De-Multiplexer
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SISO and SIPO

SISO and SIPO
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Full Adder

Full Adder
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Half Adder

Half Adder
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NOT Gate

NOT Gate
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1x8 De-multiplexers

1x8 De-multiplexers
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Priority Encoder

Priority Encoder
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1X4 De-Multiplexer

1X4 De-Multiplexer
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OR Gate

OR Gate
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Half Subtractor

Half Subtractor
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Gray to Binary

Gray to Binary
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Arithmetic logic unit

Arithmetic logic unit
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Arithmetic logic unit

Arithmetic logic unit
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SR and D Flip FLop using NAND

SR and D Flip FLop using NAND
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4X1 MUX

4X1 MUX
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1x4 De-multiplexers

1x4 De-multiplexers
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Full Subtractor

Full Subtractor
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AND Gate

AND Gate
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Priority Encoder

Priority Encoder
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Utkarsh Saxena is not a collaborator of any project.

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