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Utkarsh Saxena

Member since: 726 days

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OR Gate

OR Gate
Public
OR Gate

PISO

PISO
Public
PISO

Full Subtractor

Full Subtractor
Public
Full Subtractor

NOR Gate

NOR Gate
Public
NOR Gate

1X4 De-Multiplexer

1X4 De-Multiplexer
Public
1X4 De-Multiplexer

8X1 Multiplexer Assesment

8X1 Multiplexer Assesment
Public
8X1 Multiplexer Assesment

SR and D Flip FLop using NAND

SR and D Flip FLop using NAND
Public
SR and D Flip FLop using NAND

Priority Encoder

Priority Encoder
Public
Priority Encoder

Priority Encoder

Priority Encoder
Public
Priority Encoder

4X1 MUX

4X1 MUX
Public
4X1 MUX

1x8 De-multiplexers

1x8 De-multiplexers
Public
1x8 De-multiplexers

8X1 MUX

8X1 MUX
Public
8X1 MUX

XNOR Gate

XNOR Gate
Public
XNOR Gate

Arithmetic logic unit

Arithmetic logic unit
Public
Arithmetic logic unit

4X1 Multiplexer

4X1 Multiplexer
Public
4X1 Multiplexer

N -Parallel Subtractor

N -Parallel Subtractor
Public
N -Parallel Subtractor

Arithmetic logic unit

Arithmetic logic unit
Public
Arithmetic logic unit

Half Subtractor

Half Subtractor
Public
Half Subtractor

AND Gate

AND Gate
Public
AND Gate

XOR Gate

XOR Gate
Public
XOR Gate

Priority Encoder

Priority Encoder
Public
Priority Encoder

Gray to Binary

Gray to Binary
Public
Gray to Binary

1x4 De-multiplexers

1x4 De-multiplexers
Public
1x4 De-multiplexers

3 - Bit Parallel Adder

3 - Bit Parallel Adder
Public
3 - Bit Parallel Adder

Binary To Gray Code

Binary To Gray Code
Public
Binary To Gray Code

PIPO

PIPO
Public
PIPO

NAND Gate

NAND Gate
Public
NAND Gate

Priority Encoder

Priority Encoder
Public
Priority Encoder

Arithmetic logic unit

Arithmetic logic unit
Public
Arithmetic logic unit

1X8 De-Multiplexer

1X8 De-Multiplexer
Public
1X8 De-Multiplexer

SISO and SIPO

SISO and SIPO
Public
SISO and SIPO

4X1 MUX

4X1 MUX
Public
4X1 MUX

Full Adder

Full Adder
Public
Full Adder

Half Adder

Half Adder
Public
Half Adder

NOT Gate

NOT Gate
Public
NOT Gate
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