Utkarsh Saxena
Member since: 726 days
Educational Institution:
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OR Gate
OR Gate
Public
PISO
PISO
Public
Full Subtractor
Full Subtractor
Public
NOR Gate
NOR Gate
Public
1X4 De-Multiplexer
1X4 De-Multiplexer
Public
8X1 Multiplexer Assesment
8X1 Multiplexer Assesment
Public
SR and D Flip FLop using NAND
SR and D Flip FLop using NAND
Public
Priority Encoder
Priority Encoder
Public
Priority Encoder
Priority Encoder
Public
4X1 MUX
4X1 MUX
Public
1x8 De-multiplexers
1x8 De-multiplexers
Public
8X1 MUX
8X1 MUX
Public
XNOR Gate
XNOR Gate
Public
Arithmetic logic unit
Arithmetic logic unit
Public
4X1 Multiplexer
4X1 Multiplexer
Public
N -Parallel Subtractor
N -Parallel Subtractor
Public
Arithmetic logic unit
Arithmetic logic unit
Public
Half Subtractor
Half Subtractor
Public
AND Gate
AND Gate
Public
XOR Gate
XOR Gate
Public
Priority Encoder
Priority Encoder
Public
Gray to Binary
Gray to Binary
Public
1x4 De-multiplexers
1x4 De-multiplexers
Public
3 - Bit Parallel Adder
3 - Bit Parallel Adder
Public
Binary To Gray Code
Binary To Gray Code
Public
PIPO
PIPO
Public
NAND Gate
NAND Gate
Public
Priority Encoder
Priority Encoder
Public
Arithmetic logic unit
Arithmetic logic unit
Public
1X8 De-Multiplexer
1X8 De-Multiplexer
Public
SISO and SIPO
SISO and SIPO
Public
4X1 MUX
4X1 MUX
Public
Full Adder
Full Adder
Public
Half Adder
Half Adder
Public
NOT Gate
NOT Gate
Public
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