NITIN GUPTA
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EXP-17
EXP-17
Untitled
Untitled
Untitled
Untitled
1*8
1*8
D latch
D latch
ex5
ex5
ass2
ass2
Ex-14(A)
Ex-14(A)
E4
E4
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
2*2 bit multiplier
2*2 bit multiplier
Left Shift
Left Shift
14 B
14 B
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
15 B
15 B
RiGHT Shift
RiGHT Shift
1*4 Demultiplexer
1*4 Demultiplexer
p3
p3
D latch
D latch
3*3 multiplier
3*3 multiplier
Internal Assesment (3-bit Carry look adder)
Internal Assesment (3-bit Carry look adder)
Untitled
Untitled
Experiment 1
Experiment 1
EXP4
EXP4
MULTIPLEXER 4*1 AND 8*1
MULTIPLEXER 4*1 AND 8*1
8*1
8*1
Universal Shift
Universal Shift
Untitled
Untitled
Untitled
Untitled
J-K FLIP-FLOP
J-K FLIP-FLOP
kmap
kmap
1*8
1*8
3*3multiplier
3*3multiplier
FLIP FLOP
FLIP FLOP
E4
E4
1*8 DEMULTIPLEXER
1*8 DEMULTIPLEXER
Internal Assesment (3-bit Carry look adder)
Internal Assesment (3-bit Carry look adder)
MASTER SLAVE D FILP FLOP
MASTER SLAVE D FILP FLOP
Untitled
Untitled
J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
2*4 and 3*8
2*4 and 3*8
CONTROLLED SR LATCH
CONTROLLED SR LATCH
15_A
15_A
Experiment 1
Experiment 1
EX 16
EX 16
J-K FLIP-FLOP
J-K FLIP-FLOP
SR LATCH
SR LATCH
TIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
TIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
1*4 Demultiplexer
1*4 Demultiplexer
Untitled
Untitled
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