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EXP-17
EXP-17Untitled
UntitledUntitled
Untitled1*8
1*8ex5
ex5ass2
ass2Ex-14(A)
Ex-14(A)E4
E42*2 bit multiplier
2*2 bit multiplier14 B
14 B15 B
15 BRiGHT Shift
RiGHT Shift1*4 Demultiplexer
1*4 Demultiplexerp3
p3D latch
D latch3*3 multiplier
3*3 multiplierInternal Assesment (3-bit Carry look adder)
Internal Assesment (3-bit Carry look adder)Untitled
UntitledExperiment 1
Experiment 1EXP4
EXP48*1
8*1Universal Shift
Universal ShiftUntitled
UntitledUntitled
Untitledkmap
kmap1*8
1*83*3multiplier
3*3multiplierFLIP FLOP
FLIP FLOPE4
E41*8 DEMULTIPLEXER
1*8 DEMULTIPLEXERInternal Assesment (3-bit Carry look adder)
Internal Assesment (3-bit Carry look adder)MASTER SLAVE D FILP FLOP
MASTER SLAVE D FILP FLOPJ-K FLIP-FLOP
J-K FLIP-FLOPUntitled
UntitledJ-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)2*4 and 3*8
2*4 and 3*8CONTROLLED SR LATCH
CONTROLLED SR LATCH15_A
15_AExperiment 1
Experiment 1J-K FLIP-FLOP
J-K FLIP-FLOPMULTIPLEXER 4*1 AND 8*1
MULTIPLEXER 4*1 AND 8*1D latch
D latchDesign of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1sSR LATCH
SR LATCHTIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
TIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)1*4 Demultiplexer
1*4 DemultiplexerUntitled
UntitledDesign of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Design of Clocked sequenctial circuit to detect 3 or more consequetive 1sEX 16
EX 16Left Shift
Left Shift