project.name

NITIN GUPTA

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

EXP-17

EXP-17
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

1*8

1*8
Public
project.name

ex5

ex5
Public
project.name

ass2

ass2
Public
project.name

Ex-14(A)

Ex-14(A)
Public
project.name

E4

E4
Public
project.name

2*2 bit multiplier

2*2 bit multiplier
Public
project.name

14 B

14 B
Public
project.name

15 B

15 B
Public
project.name

RiGHT Shift

RiGHT Shift
Public
project.name

1*4 Demultiplexer

1*4 Demultiplexer
Public
project.name

p3

p3
Public
project.name

D latch

D latch
Public
project.name

3*3 multiplier

3*3 multiplier
Public
project.name

Internal Assesment (3-bit Carry look adder)

Internal Assesment (3-bit Carry look adder)
Public
project.name

Untitled

Untitled
Public
project.name

Experiment 1

Experiment 1
Public
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EXP4

EXP4
Public
project.name

8*1

8*1
Public
project.name

Universal Shift

Universal Shift
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

kmap

kmap
Public
project.name

1*8

1*8
Public
project.name

3*3multiplier

3*3multiplier
Public
project.name

FLIP FLOP

FLIP FLOP
Public
project.name

E4

E4
Public
project.name

1*8 DEMULTIPLEXER

1*8 DEMULTIPLEXER
Public
project.name

Internal Assesment (3-bit Carry look adder)

Internal Assesment (3-bit Carry look adder)
Public
project.name

MASTER SLAVE D FILP FLOP

MASTER SLAVE D FILP FLOP
Public
project.name

J-K FLIP-FLOP

J-K FLIP-FLOP
Public
project.name

Untitled

Untitled
Public
project.name

J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)

J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
Public
project.name

2*4 and 3*8

2*4 and 3*8
Public
project.name

CONTROLLED SR LATCH

CONTROLLED SR LATCH
Public
project.name

15_A

15_A
Public
project.name

Experiment 1

Experiment 1
Public
project.name

J-K FLIP-FLOP

J-K FLIP-FLOP
Public
project.name

MULTIPLEXER 4*1 AND 8*1

MULTIPLEXER 4*1 AND 8*1
Public
project.name

D latch

D latch
Public
project.name

Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s

Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Public
project.name

SR LATCH

SR LATCH
Public
project.name

TIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)

TIMING DIAGRAM 26J-K FLIP-FLOP USING D FLIP FLOP(EDGE TRIGGERED)
Public
project.name

1*4 Demultiplexer

1*4 Demultiplexer
Public
project.name

Untitled

Untitled
Public
project.name

Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s

Design of Clocked sequenctial circuit to detect 3 or more consequetive 1s
Public
project.name

EX 16

EX 16
Public
project.name

Left Shift

Left Shift
Public
project.name
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