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Clocked SR latch using NOR & NAND gate
Clocked SR latch using NOR & NAND gateExp-12
Exp-12Exp 17a ii (shift left using JK)
Exp 17a ii (shift left using JK)Exp 15-a (2 bit arithmetic)
Exp 15-a (2 bit arithmetic)Exp 14-a
Exp 14-a23/09/2020
23/09/2020Exp.6 (1)
Exp.6 (1)Exp. 7(1)
Exp. 7(1)2x4 decoder
2x4 decoderExp 17c (universal shift register)
Exp 17c (universal shift register)Exp 15-b (logic diagram)
Exp 15-b (logic diagram)Lab 3
Lab 3Exp-11
Exp-11Exp 17 b2 (shift right using JK)
Exp 17 b2 (shift right using JK)8x1 MULTIPLEXER
8x1 MULTIPLEXERExp 16
Exp 161x8 DeMultiplexer
1x8 DeMultiplexerDecoder 3x8
Decoder 3x8Master Slave Exp-13
Master Slave Exp-13JK Flip Flop Exp-13
JK Flip Flop Exp-13Exp 14-b
Exp 14-bExp 17 b1 (Shift right using D)
Exp 17 b1 (Shift right using D)2x2 multiplier LAB Assignment
2x2 multiplier LAB Assignment4x1 MULTIPLEXER
4x1 MULTIPLEXER26/08/12
26/08/12Untitled
UntitledLab 3
Lab 3Lab 2
Lab 2Exp.6 (2)
Exp.6 (2)Untitled
UntitledD latch NOR and NAND gate
D latch NOR and NAND gate1x4 DeMultiplexer
1x4 DeMultiplexerExp 17a i (shift left using D)
Exp 17a i (shift left using D)Logic Gates
Logic Gates2/9/2020
2/9/2020