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Exp 3
Exp 3Experiment_10
Experiment_10EXPERIMENT 5
EXPERIMENT 5Exp-15-B
Exp-15-BShift-right-jk
Shift-right-jkEXP_14
EXP_14EXP 6_3X3_BIT_Multiplier
EXP 6_3X3_BIT_MultiplierEXPERIMENT-7
EXPERIMENT-7Internal_Assessment_4x1 and 8x1 Demultiplexer
Internal_Assessment_4x1 and 8x1 DemultiplexerExperiment 4_carry lookahead_adder
Experiment 4_carry lookahead_adderEXP_17_C
EXP_17_CClocked S-R latch using NOR
Clocked S-R latch using NORExperiment 6
Experiment 6Exp 15 _ALU
Exp 15 _ALUExperiment 8_3 X 8_decoder
Experiment 8_3 X 8_decoderD latch using NOR
D latch using NORMASTER-SLAVE_EXP-13
MASTER-SLAVE_EXP-13Shift-right-D
Shift-right-DShift-Left-D
Shift-Left-D3 Continous 1s
3 Continous 1sExperiment 3
Experiment 3Half & full addder(external)
Half & full addder(external)Experiment9_Multiplexer8x1
Experiment9_Multiplexer8x1JK FLIP FLOP USING D FLIP FLOP
JK FLIP FLOP USING D FLIP FLOPExperiment 8_2X4 DECODER
Experiment 8_2X4 DECODERExperiment_10_1x8
Experiment_10_1x8Exp-17_Shift-left-jk
Exp-17_Shift-left-jkExperiment_9_Multiplexer4x1
Experiment_9_Multiplexer4x114 B exp
14 B expExp 11 (clocked S-R Latch and D latch )
Exp 11 (clocked S-R Latch and D latch )Modified S-R circuit
Modified S-R circuitInternal-D-flipflop
Internal-D-flipflop