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MAYANK JAIN

Member since: 3 years

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Exp 3

Exp 3
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Experiment_10

Experiment_10
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EXPERIMENT 5

EXPERIMENT 5
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Exp-15-B

Exp-15-B
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Shift-right-jk

Shift-right-jk
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EXP_14

EXP_14
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EXP 6_3X3_BIT_Multiplier

EXP 6_3X3_BIT_Multiplier
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EXPERIMENT-7

EXPERIMENT-7
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Internal_Assessment_4x1 and 8x1 Demultiplexer

Internal_Assessment_4x1 and 8x1 Demultiplexer
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Experiment 4_carry lookahead_adder

Experiment 4_carry lookahead_adder
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EXP_17_C

EXP_17_C
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Clocked S-R latch using NOR

Clocked S-R latch using NOR
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Experiment 6

Experiment 6
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Exp 15 _ALU

Exp 15 _ALU
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Experiment 8_3 X 8_decoder

Experiment 8_3 X 8_decoder
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D latch using NOR

D latch using NOR
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MASTER-SLAVE_EXP-13

MASTER-SLAVE_EXP-13
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Shift-right-D

Shift-right-D
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Shift-Left-D

Shift-Left-D
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3 Continous 1s

3 Continous 1s
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Experiment 3

Experiment 3
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Half & full addder(external)

Half & full addder(external)
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Experiment9_Multiplexer8x1

Experiment9_Multiplexer8x1
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JK FLIP FLOP USING D FLIP FLOP

JK FLIP FLOP USING D FLIP FLOP
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Experiment 8_2X4 DECODER

Experiment 8_2X4 DECODER
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Experiment_10_1x8

Experiment_10_1x8
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Exp-17_Shift-left-jk

Exp-17_Shift-left-jk
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Experiment_9_Multiplexer4x1

Experiment_9_Multiplexer4x1
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14 B exp

14 B exp
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Exp 11 (clocked S-R Latch and D latch )

Exp 11 (clocked S-R Latch and D latch )
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Modified S-R circuit

Modified S-R circuit
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Internal-D-flipflop

Internal-D-flipflop
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MAYANK JAIN is not a collaborator of any project.

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