project.name

mansi kumari

Member since: 4 years

Educational Institution: GLA UNIVERSITY

Country: India

syncronous up counter

syncronous up counter
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Untitled

Untitled
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subtractor using full adder

subtractor using full adder
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mod 4 syncronous up counter

mod 4 syncronous up counter
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ALU

ALU
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MUX

MUX
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half subtractor using EXOR,AND,NOT gates

half subtractor using EXOR,AND,NOT gates
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BCD DECODER CIRCUIT

BCD DECODER CIRCUIT
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full adder with using EXOR gate

full adder with using EXOR gate
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half subtractor using EXOR,AND,NOT gates

half subtractor using EXOR,AND,NOT gates
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BINARY CODED DECIMAL DECODER 7 SEGMENT DISPLAY OUTPUT DEVICE

BINARY CODED DECIMAL DECODER 7 SEGMENT DISPLAY OUTPUT DEVICE
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half adder

half adder
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gates

gates
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Untitled

Untitled
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full subtractor usnig two half subtractor

full subtractor usnig two half subtractor
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ADDER

ADDER
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4 BIT PIPO SHIFT REGISTER

4 BIT PIPO SHIFT REGISTER
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4 BIT SISO SHIFT REGISTER

4 BIT SISO SHIFT REGISTER
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BCD DECODER CIRCUIT

BCD DECODER CIRCUIT
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4 BIT SIPO SHIFT REGISTER

4 BIT SIPO SHIFT REGISTER
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half subtractor using EXOR,AND,NOT gates

half subtractor using EXOR,AND,NOT gates
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