project.name

Somya Mangla

Member since: 4 years

Educational Institution: Not Entered

Country: Not Entered

project

project
Public
project.name

final

final
Public
project.name

final

final
Public
project.name

final

final
Public
project.name

Logic Unit Using Multiplexer

Logic Unit Using Multiplexer
Public
project.name

final

final
Public
project.name

priority

priority
Public
project.name

priority

priority
Public
project.name

ALU

ALU
Public
project.name

8 bit and 4 bit\

8 bit and 4 bit\
Public
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subtractor

subtractor
Public
project.name

FULL ADDER

FULL ADDER
Public
project.name

d flip flop

d flip flop
Public
project.name

1st

1st
Public
project.name

final

final
Public
project.name

final

final
Public
project.name

FULL ADDER

FULL ADDER
Public
project.name

Untitled

Untitled
Public
project.name

final

final
Public
project.name

project

project
Public
project.name

JHA

JHA
Public
project.name

Untitled

Untitled
Public
project.name

Logic unit using Multiplexer

Logic unit using Multiplexer
Public
project.name

8:3 Priority Encoder Using 4:2 Priority Encoder

8:3 Priority Encoder Using 4:2 Priority Encoder
Public
project.name

priority

priority
Public
project.name

final

final
Public
project.name

lab

lab
Public
project.name

Untitled

Untitled
Public
project.name

Untitled

Untitled
Public
project.name

full adder

full adder
Public
project.name

priority

priority
Public
project.name

8:3 Priority Encoder Using 4:2 Priority Encoder

8:3 Priority Encoder Using 4:2 Priority Encoder
Public
project.name
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