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saurabh jain

Member since: 4 years

Educational Institution: Not Entered

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8 REGISTERS

8 REGISTERS
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Priority Encoder

Priority Encoder
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PRIORITY ENCODER

PRIORITY ENCODER
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4-16 DECODER

4-16 DECODER
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2-BIT-COMPARATOR

2-BIT-COMPARATOR
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4-bit full adder circuit

4-bit full adder circuit
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FULL ADDER

FULL ADDER
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2-BIT-COMPARATOR

2-BIT-COMPARATOR
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full adder using nand gate

full adder using nand gate
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Half-Adder

Half-Adder
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full and half adder using MUX

full and half adder using MUX
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AIRTHEMETIC LOGIC OPERATIONAS

AIRTHEMETIC LOGIC OPERATIONAS
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BINARY A AND D

BINARY A AND D
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x+yz;a or b and control;a or b

x+yz;a or b and control;a or b
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TRISTATE

TRISTATE
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half adder using nand gates

half adder using nand gates
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DECODER LOGIC OPERATIONS

DECODER LOGIC OPERATIONS
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gates

gates
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2-BIT-COMPARATOR

2-BIT-COMPARATOR
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saurabh jain is not a collaborator of any project.

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