Member since: 4 years
Educational Institution: GLA University Mathura
Country: India
4 Bit SIPO Shify Register
4 Bit SIPO Shify RegisterExperiment 5 : Half and Full Subtractor
Experiment 5 : Half and Full SubtractorExperiment 4 - Half Adder and Full Adder
Experiment 4 - Half Adder and Full AdderExperiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND Gate
Experiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND GateExperiment 1 - Implementation of Basic gates
Experiment 1 - Implementation of Basic gatesExperiment 3 - Implementation Of Basic Gates (NOT, OR, AND, XOR) Using NOR Gate
Experiment 3 - Implementation Of Basic Gates (NOT, OR, AND, XOR) Using NOR GateBCD counter
BCD counter