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sajal sharma

Member since: 4 years

Educational Institution: GLA University Mathura

Country: India

4 Bit SIPO Shify Register

4 Bit SIPO Shify Register
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Experiment 5 : Half and Full Subtractor

Experiment 5 : Half and Full Subtractor
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Experiment 4 - Half Adder and Full Adder

Experiment 4 - Half Adder and Full Adder
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Experiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND Gate

Experiment 2 - Implementation of Basic Gates (NOT, AND, OR, XOR) using NAND Gate
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Experiment 1 - Implementation of Basic gates

Experiment 1 - Implementation of Basic gates
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Experiment 3 - Implementation Of Basic Gates (NOT, OR, AND, XOR) Using NOR Gate

Experiment 3 - Implementation Of Basic Gates (NOT, OR, AND, XOR) Using NOR Gate
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BCD counter

BCD counter
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